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SSM3582ACPZ-R7 数据表(PDF) 12 Page - Analog Devices

部件名 SSM3582ACPZ-R7
功能描述  2×, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier
PDF  58 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM3582ACPZ-R7 数据表(HTML) 12 Page - Analog Devices

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SSM3582A
Data Sheet
Rev. A | Page 12 of 58
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
PGND
2
PGND
3
AVDD_EN
NOTES
1. USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD
TO THE GROUND PLANE ON THE PCB.
4
SCL
5
SDA
6
FSYNC
7
SDATA
8
BCLK
9
PGND
10
PGND
23 DVDD_EN
24 AVDD
25 AGND
26 ADDR0
27 ADDR1
28 DVDD
29 PGND
30 PGND
22 PGND
21 PGND
SSM3582A
TOP VIEW
(Not to Scale)
Figure 6. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
PGND
PWR
Left Channel Power Stage Ground.
2
PGND
PWR
Left Channel Power Stage Ground.
3
AVDD_EN
AIN
5 V AVDD Regulator Enable. Connect this pin to PVDD to enable the AVDD regulator or connect to AGND
to disable the regulator. When this pin is connected to PVDD, the regulator is enabled. When this pin is
connected to AGND, the regulator is disabled.
4
SCL
DIN
I2C Clock Input.
5
SDA
DIO
I2C Data.
6
FSYNC
DIN
I2S/TDM Frame Sync Input.
7
SDATA
DIN
I2S/TDM Serial Data Input.
8
BCLK
DIN
I2S/TDM Bit Clock Input.
9
PGND
PWR
Right Channel Power Stage Ground.
10
PGND
PWR
Right Channel Power Stage Ground.
11
BSTR+
AIN
Bootstrap Input, Right Channel Noninverting.
12
OUTR+
AOUT
Right Channel Noninverting Output.
13
OUTR+
AOUT
Right Channel Noninverting Output.
14
PVDD
PWR
Right Channel Power Stage Supply.
15
PVDD
PWR
Right Channel Power Stage Supply.
16
PVDD
PWR
Right Channel Power Stage Supply.
17
PVDD
PWR
Right Channel Power Stage Supply.
18
OUTR−
AOUT
Right Channel Inverting Output.
19
OUTR−
AOUT
Right Channel Inverting Output.
20
BSTR−
AIN
Bootstrap Input, Right Channel Inverting.
21
PGND
PWR
Right Channel Power Stage Ground.
22
PGND
PWR
Right Channel Power Stage Ground.
23
DVDD_EN
AIN
1.8 V DVDD Regulator Enable. Connect this pin to AVDD to enable the DVDD regulator or connect to
AGND to disable the regulator. When this pin is connected to AVDD, the regulator is enabled. When this
pin is connected to AGND, the regulator is disabled.
24
AVDD
PWR
Analog Supply 5 V Regulator Output/External 5 V Input.
25
AGND
PWR
Analog Ground.
26
ADDR0
AIN
Address Select 0 (See Table 14).
27
ADDR1
AIN
Address Select 1 (See Table 14).



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