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SSM3582ACPZ-R7 数据表(PDF) 29 Page - Analog Devices

部件名 SSM3582ACPZ-R7
功能描述  2×, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier
PDF  58 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM3582ACPZ-R7 数据表(HTML) 29 Page - Analog Devices

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Data Sheet
SSM3582A
Rev. A | Page 29 of 58
I2C Read and Write Operations
Figure 72 shows the timing of a single-word write operation.
Every ninth clock, the SSM3582A issues an acknowledge by
pulling SDA low.
Figure 73 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The SSM3582A knows to increment its
subaddress register every byte because the requested subaddress
corresponds to a register or memory area with a byte word
length.
The timing of a single-word read operation is shown in Figure 74.
Note that the first R/W bit is 0, indicating a write operation,
because the subaddress must still be written to set up the internal
address. After the SSM3582A acknowledges the receipt of the
subaddress, the master must issue a repeated start command,
followed by the chip address byte with the R/W set to 1 (read).
This repeated command causes the SSM3582A SDA to reverse
and to begin driving data back to the master. The master then
responds every ninth pulse with an acknowledge pulse to the
SSM3582A. Refer to Table 17 for a list of abbreviations in Figure 72
through Figure 75.
Table 17. Abbreviations for Figure 72 Through Figure 75
Symbol
Meaning
S
Start bit
P
Stop bit
AM
Acknowledge (ACK used in Figure 72 through Figure 75) by master
AS
Acknowledge (ACK used in Figure 72 through Figure 75) by slave
R/W
SCL
SDA
SDA
(CONTINUED)
SCL
(CONTINUED)
START BY
MASTER
FRAME1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE
FRAME 3
DATA BYTE 1
FRAME 4
DATA BYTE 2
STOP BY
MASTER
ACK
ACK
ACK
ACK
Figure 71. I2C Read/Write Timing
START
BIT
STOP
BIT
R/W
= 0
ACK BY
SLAVE
ACK BY
SLAVE
IC ADDRESS
(7 BITS)
SUBADDRESS
(8 BITS)
DATA BYTE 1
(8 BITS)
Figure 72. Single-Word I2C Write Format
S
CHIP ADDRESS,
R/W = 0
AS
AS
AS
AS
SUBADDRESS
DATA-
WORD 1
DATA-
WORD 2
P
Figure 73. Burst Mode I2C Write Format
S
CHIP
ADDRESS,
R/W = 0
CHIP
ADDRESS,
R/W = 1
AS
AS
AS
AM
SUBADDRESS
DATA
BYTE 1
P
DATA
BYTE N
S
Figure 74. Single-Word I2C Read Format
S
CHIP
ADDRESS,
R/W = 0
CHIP
ADDRESS,
R/W = 1
AS
AS
AS
AM
SUBADDRESS
DATA-
WORD 1
P
...
S
Figure 75. Burst Mode I2C Read Format



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