SSM3582ACPZ-R7 datasheet(31/58 Pages) AD

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Data Sheet

SSM3582A

Rev. A | Page 31 of 58

MONO MODE

The SSM3582A can be operated in mono mode for driving low

impedance loads. In mono mode, the left and right power stages

can be connected in parallel, as shown in Figure 87. Use caution

when setting up mono mode. For proper operation, any hardware

changes are required along with setting the register. For mono

mode operation, set the MONO bit (Register 0x04, Bit 4) to 1. By

default, this bit is set to 0 for stereo mode. After the bit is set for

mono mode, only the left channel modulator is active and it feeds

both the left and right channel power stages. The OUTL+ and

OUTR+ pins are in phase. The OUTL− and OUTR− pins are

also in phase. For mono mode, OUTL+ must be shorted to

OUTR+. Similarly, OUTL− must be shorted to OUTR−. Note

that the resistance of the short must be <10 mΩ. If the short

resistance is higher than 10 mΩ, the THD + N performance

degrades. Refer to the EVAL-SSM3582Z user guide for more

information.

In standalone mode, the ADDR0, ADDR1, SCL, and SDA pins

determine the TDM slot. See the Table 18 for the possible TDM

slot configurations in mono mode.

ANALOG AND DIGITAL GAIN

Four different gain settings are available to optimize the dynamic

range of the amplifier in relation to the PVDD supply voltage.

In software mode, the initial 19 dB gain setting can be updated

through the control interface. In standalone mode, the I2C

interface pins set the gain of the device. Table 19 summarizes

the gain settings and load drive characteristics of the amplifier.

The amplifier analog gain is set prior to enabling the device

outputs and must not be changed during operation. A proper

mute/unmute sequence is required to prevent audible transients

between gain settings.

Finer level control is available in the digital domain, with a very

flexible −70 dB to +24 dB, 0.375 dB/step ramp volume control

and selectable nonaliasing clipping point. The digital volume

control also includes a playback level limiter that can be set in

tandem with the battery voltage monitor to prevent the amplifier

from browning out the system when battery level is critically low.

POP AND CLICK SUPPRESSION

Pops and clicks are undesirable audible transients generated by

the amplifier system that do not come from the system input

signal. Voltage transients as small as 10 mV can be heard as an

audible pop in the speaker. Voltage transients at the output of

audio amplifiers often occur when shutdown is activated or

deactivated. The SSM3582A has a pop and click suppression

architecture that reduces these output transients, resulting in

noiseless activation and deactivation. Set either mute or power-

down before BCLK is removed to ensure a pop free experience.

TEMPERATURE SENSOR

The SSM3582A contains an 8-bit ADC that measures the die

temperature of the device and is enabled via the TEMP_PWDN bit

in Register 0x04. After the sensor is enabled, the temperature

can be read via the I2C in the TEMP register, Register 0x1B. The

temperature information is stored in Register 0x1B in an 8-bit,

unsigned format. The ADC input range is fixed internally from

−60°C to +195°C. To convert the hexadecimal value to the

temperature (Celsius) value, use the following steps:

1. Convert the hexadecimal value to decimal and then

subtract 60. For example, if the hexadecimal value is 0x54,

the decimal value is 84.

2. Calculate the temperature using the following equation:

Temperature = Decimal Value − 60

With a decimal value of 84,

Temperature = 84 − 60 = 24°C

Table 19. Analog Gain Settings and Drive Characteristics

ANA_GAIN

Gain (dB)

Output Voltage (VOUT)

Bit 1

Bit 0

RMS (V rms)

Peak (V)

4.38

6.2

6.18

8.75

8.83

12.5

11.22

15.5

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