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SSM3582ACPZ-R7 数据表(PDF) 9 Page - Analog Devices

部件名 SSM3582ACPZ-R7
功能描述  2×, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier
PDF  58 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM3582ACPZ-R7 数据表(HTML) 9 Page - Analog Devices

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Data Sheet
SSM3582A
Rev. A | Page 9 of 58
DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 7.
Limit
Parameter
Min
Max
Unit
Description
I2C PORT
fSCL
400
kHz
SCL frequency
tSCLH
0.26
µs
SCL high
tSCLL
0.5
µs
SCL low
tSCS
0.26
µs
Setup time; relevant for repeated start condition
tSCH
0.26
µs
Hold time; after this period, the first clock is generated
tDS
50
ns
Data setup time
tDH
0.14
µs
Data hold time
tSCR
120
ns
SCL rise time
tSCF
120
ns
SCL fall time
tSDR
120
ns
SDA rise time
tSDF
120
ns
SDA fall time
tBFT
0.5
µs
Bus free time (time between stop and start)
DIGITAL INPUT TIMING SPECIFICATIONS
Table 8.
Limit
Parameter
Min
Max
Unit
Description
SERIAL PORT
tBIL
10
ns
BCLK low pulse width
tBIH
10
ns
BCLK high pulse width
tSIS
4
ns
SDATA setup; time to BCLK rising
tSIH
4
ns
SDATA hold; time from BCLK rising
tLIS
5
ns
FSYNC setup time to BCLK rising
tLIH
5
ns
FSYNC hold time to BCLK rising
tBP
20
ns
Minimum BCLK period
Digital Timing Diagrams
tSCH
tSCS
tBFT
tSCF
tDS
tSCLL
tSCR
tDH
tSCLH
tSCH
STOP
CONDITION
START
CONDITION
SDA
SCL
tSDF
tSDR
Figure 2. I2C Port Timing



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