SSM3582ACPZ-R7 datasheet(36/58 Pages) AD

36 / 58 page

SSM3582A

Data Sheet

Rev. A | Page 36 of 58

BOOTSTRAP CAPACITORS

The output stage of the SSM3582A uses a high-side NMOS

driver, rather than a PMOS driver. To generate the gate drive

voltage for the high-side NMOS, a bootstrap capacitor for each

output terminal acts as a floating power supply for the switching

cycle. Use 0.22 μF capacitors to connect the appropriate output pin

(OUTx±) to the bootstrap pin (BSTx±). For example, connect a

0.22 μF capacitor between OUTL+ (a left channel, noninverting

output) and BSTL+ for bootstrapping the left channel. Similarly,

connect another 0.22 μF capacitor between the OUTL− and

BSTL− pins for the left channel inverting output.

POWER SUPPLY DECOUPLING

To ensure high efficiency, low THD, and high PSRR, proper

power supply decoupling is necessary. Noise transients on the

power supply lines are short duration voltage spikes. These spikes

can contain frequency components that extend into the hundreds

of megahertz. The power supply input must be decoupled with

a good quality, low ESL, low ESR bulk capacitor larger than 220 µF.

This capacitor bypasses low frequency noise to the ground

plane. For high frequency decoupling, place 1 µF capacitors as

close as possible to the PVDD pins of the device.

OUTPUT EMI FILTERING

Additional EMI filtering may be required when the speaker

traces and cables are long and present a significant capacitive

load that can create additional draw from the amplifier. Typical

power ferrites present a significant magnetic hysteresis cycle

that affects THD performance and are not recommended for

high performance designs. The NFZ filter series from Murata,

designed in close collaboration with Analog Devices, Inc.,

provides a closed hysteresis loop similar to an air coil with

minimum impact on performance. Products are available at

upwards of 4 A rms, well suited to this application. A small

capacitor can be added between the output of the filter and

ground to further attenuate very high frequencies. Take care

to ensure the capacitor is properly sized to avoid affecting idle

power consumption or efficiency.

PCB PLACEMENT

Component selection and placement influence greatly on

system performance, both measured and subjective. Proper

PVDD layout and decoupling is necessary to reach the specified

level of performance, particularly at the highest power levels.

The placement shown in Figure 85 ensures proper output stage

decoupling for each channel, for minimum supply noise and

maximum separation between channels. Additional bulk

decoupling is necessary to reduce current ripple at low

frequencies, and can be shared between several amplifiers

in a multichannel solution.

BSTL+

0.22µF CAPACITOR

PVDD DECOUPLING

0.1µF CAPACITOR

BSTL–

0.22µF CAPACITOR

DVDD DECOUPLING

0.1µF CAPACITOR

AVDD DECOUPLING

0.1µF CAPACITOR

BSTR+

0.22µF CAPACITOR

BSTR–

0.22µF CAPACITOR

PVDD DECOUPLING

0.1µF CAPACITOR

Figure 85. Recommended Component Placement

SSM3582ACPZ-R7 数据表(PDF) 36 Page - Analog Devices

SSM3582ACPZ-R7 数据表(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载

链接网址

SSM3582ACPZ-R7 数据表(PDF) 36 Page - Analog Devices

SSM3582ACPZ-R7 数据表(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表 下载

链接网址

数据表下载