SSM3582ACPZ-R7 datasheet(27/58 Pages) AD

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Data Sheet

SSM3582A

Rev. A | Page 27 of 58

Table 13. Supported BCLK Rates in MHz1

Sample

Rate (kHz)

BCLK (MHz)/FSYNC Ratio2

100

128

192

200

256

384

512

768

800

1024

2048

4096

8 to 12

N/A

Yes

16 to 24

N/A

Yes

N/A

32 to 48

Yes

N/A

64 to 96

Yes

N/A

128 to 192

Yes

N/A

Yes means that the specified rate is supported and N/A means not applicable.

BCLK = (BCLK/FSYNC ratio) × sample rate.

I2C Control

The SSM3582A supports an I2C-compatible, 2-wire serial bus,

shared across multiple peripherals. Two signals, serial data

(SDA) and serial clock (SCL), carry information between the

SSM3582A and the system I2C master controller. The SSM3582A

is always a slave on the bus, and cannot initiate a data transfer.

Each slave device is identified by a unique address. The address

byte format is shown in Table 14. The address resides in the

first seven bits of the I2C write. The LSB of this byte sets either a

read or write operation. Logic Level 1 corresponds to a read

operation and Logic Level 0 corresponds to a write operation.

For device address settings, see Table 16.

Table 14. I2C Device Address Byte Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

Bit 0

Bit 3

Bit 2

ADDR0

ADDR1

R/W

Both SDA and SCL are open drain, and require pull-up resistors to

the input/output voltage. The SSM3582A operates within the I2C

voltage range of 1.6 V to 3.6 V.

Addressing

Initially, each device on the I2C bus is in an idle state, monitoring

the SDA and SCL lines for a start condition and the proper

address. The I2C master initiates a data transfer by establishing

a start condition, defined by a high to low transition on SDA while

SCL remains high. This start condition indicates that an address/

data stream follows. All devices on the bus respond to the start

condition and shift the next eight bits (the 7-bit address plus

the R/W bit), MSB first. The device that recognizes the

transmitted address responds by pulling the data line low

during the ninth clock pulse. This ninth bit is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and return to the idle condition. The device address

for the SSM3582A is determined by the state of the ADDRx pins.

See the Device Address Setting section for more details.

The R/W bit determines the direction of the data. A Logic 0 on

the LSB of the first byte means the master writes information to the

peripheral, whereas a Logic 1 means the master reads information

from the peripheral after writing the subaddress and repeating the

start address. A data transfer takes place until a stop condition is

encountered. A stop condition occurs when SDA transitions

from low to high while SCL is held high. The timing for the I2C

port is shown in Figure 71.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, the SSM3582A immediately

jumps to the idle condition. During a given SCL high period, issue

only one start condition, one stop condition, or a single stop

condition followed by a single start condition. If using an invalid

subaddress, the SSM3582A does not issue an acknowledge and

returns to the idle condition. If the user exceeds the highest

subaddress while in automatic increment mode, one of two

actions is taken.

In read mode, the SSM3582A outputs the highest subaddress

indicating the end of a read. A no acknowledge condition is a

condition in which the SDA line is not pulled low on the ninth

clock pulse on SCL. If the highest subaddress location is reached

while in write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by the

SSM3582A, and the device returns to the idle condition.

Device Address Setting

The device can be set at 16 different I2C addresses using the

ADDR1 and ADDR0 pins, as well as 16 hardware modes.

ADDR1 and ADDR0 are sampled during the start-up procedure.

These pins set the appropriate operating mode, the I2C address,

and the default TDM slots. The ADDRx pins can be set to five

different voltage levels, as defined in Table 15. The ADDRx pins are

referenced to the DVDD rail of the device. Connect pull-up resistors

to the internally generated DVDD rail if the regulator is used.

Table 15. ADDRx Pin Input Level Mapping

ADDRx State

Level (V)

Connected to Ground

Connected to Ground Using a 47 kΩ Resistor

0.45

Left Floating

0.9

Connected to DVDD Using a 47 kΩ Resistor

1.35

Connected to DVDD

1.8

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