SSM3582A

Data Sheet

Rev. A | Page 8 of 58

Table 4. Power Supply Current Consumption, 8 Ω + 33 µH1

Edge Rate

Control

Mode

Internal

Regulator

IPVDD

IDVDD

IAVDD

Test Conditions

PVDD = 5 V

PVDD = 12 V

PVDD = 16 V

PVDD = 1.8 V

PVDD = 5 V

Unit

Normal

Disabled

Software master power-down

0.065

0.065

0.065

2.68

7.542

µA

Automatic power-down

0.065

0.065

0.065

43.72

7.542

µA

Quiescent

2.59

5.02

6.31

0.942

6.432

mA

Enabled

Software master power-down

0.065

0.065

0.065

N/A

N/A

µA

Automatic power-down

209

286

329

N/A

N/A

µA

Quiescent

9.82

12.39

13.73

N/A

N/A

mA

Low EMI

Disabled

Software master power-down

0.065

0.065

0.065

2.68

7.542

µA

Automatic power-down

0.065

0.065

0.065

43.72

7.542

µA

Quiescent

2.57

4.86

6.02

0.942

6.232

mA

Enabled

Software master power-down

0.065

0.065

0.065

N/A

N/A

µA

Automatic power-down

209

286

329

N/A

N/A

µA

Quiescent

9.65

12.02

13.18

N/A

N/A

mA

1

N/A means not applicable.

Table 5. Power-Down Current

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

POWER-DOWN CURRENT

External AVDD = 5 V and DVDD = 1.8 V, software

master power-down, no BCLK/FSYNC

IPVDD

PVDD = 5 V

65

463

nA

PVDD = 12 V

65

744

nA

PVDD = 16 V

65

935

nA

IAVDD

AVDD = 5 V external

7.542

22.64

μA

IDVDD

DVDD = 1.8 V external

2.7

27.27

μA

DIGITAL INPUT/OUTPUT SPECIFICATIONS

Table 6.

Parameter

Min

Typ

Max

Unit

INPUT VOLTAGE1

BCLK, FSYNC, SDATA, SCL, and SDA Pins

High (VIH)

0.7 × DVDD

5.5

V

Low (VIL)

−0.3

+0.3 × DVDD

V

INPUT LEAKAGE

BCLK, FSYNC, SDATA, ADDRx, SCL, and SDA Pins

High (IIH)

1

µA

Low (IIL)

1

µA

INPUT CAPACITANCE

5

pF

OUTPUT DRIVE STRENGTH1

SDA

3

5

mA

SAMPLE RATE (FSYNC FREQUENCY)

8

192

kHz

1

The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.