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SSM3582ACPZ-R7 数据表(PDF) 32 Page - Analog Devices |
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SSM3582ACPZ-R7 数据表(HTML) 32 Page - Analog Devices |
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32 / 58 page ![]() SSM3582A Data Sheet Rev. A | Page 32 of 58 Table 20. Fault Reporting Registers Fault Type Flag Set Condition Status Reported Register PVDD Undervoltage PVDD below <3.6 V Register 0x18, Bit 7, UVLO_PVDD 5 V Regulator Undervoltage 5 V regulator voltage at AVDD < 3.6 V Register 0x18, Bit 6, UVLO_VREG Limiter/Gain Reduction Engage Left channel limiter engaged Register 0x19, Bit 3, LIM_EG_L Right channel limiter engaged Register 0x19, Bit 7, LIM_EG_R Clipping, Left Channel Left channel DAC clipping Register 0x19, Bit 2, CLIP_L Clipping, Right Channel Right channel DAC clipping Register 0x19, Bit 6, CLIP_R Output Overcurrent Left channel output current > 6 A peak Register 0x19, Bit 1, AMP_OC_L Right channel output current > 6 A peak Register 0x19, Bit 5, AMP_OC_R Die Overtemperature Die temperature > 145°C Register 0x18, Bit 1, OTF Die Overtemperature Warning Die temperature > 117°C Register 0x18, Bit 0, OTW Battery Voltage > VBAT_INF_x Battery voltage PVDD > VBAT_INF_L Register 0x19, Bit 0, BAT_WARN_L Battery voltage PVDD > VBAT_INF_R Register 0x19, Bit 4, BAT_WARN_R Table 21. Register 0x16, Register 0x17, Fault Recovery Fault Type Flag Set Condition Status Reported Register Overtemperature Warning The amount of gain reduction applied if there is an overtemperature warning for the left channel Register 0x16, Bits[1:0], OTW_GAIN_L The amount of gain reduction applied if there is an overtemperature warning for the right channel Register 0x16, Bits[5:4], OTW_GAIN_R Manual Recovery Use to attempt manual recovery in case of a fault event Register 0x17, Bit 7, MRCV Autorecovery Attempts When autorecovery from faults is used, set the number of attempts using this bit Register 0x17, Bits[5:4], MAX_AR Undervoltage Recovery can be automatic or manual Register 0x17, Bit 2, ARCV_UV Die Overtemperature Recovery can be automatic or manual Register 0x17, Bit 1, ARCV_OT Overcurrent Recovery can be automatic or manual Register 0x17, Bit 0, ARCV_OC FAULTS AND LIMITER STATUS REPORTING The SSM3582A offers comprehensive protections against the faults at the outputs and reporting to help with system design. The faults listed in Table 20 are reported using the status registers. The faults listed in Table 20 are reported in Register 0x18 and Register 0x19 and can be read via I2C by the microcontroller in the system. In the event of a fault occurrence, use Register 0x17 to control how the device reacts to the faults. When the automatic recovery mode is set, the device attempts to recover itself after the fault event and, in case the fault persists, then the device sets the fault again. This process repeats until the fault is resolved. When the manual recovery mode is used, the device shuts down and the recovery must be attempted using the system microcontroller. VBAT (PVDD) SENSING The SSM3582A contains an 8-bit ADC that measures the voltage of the battery voltage (VBAT) or PVDD supply. The battery voltage information is stored in Register 0x1A as an 8-bit unsigned format. The ADC input range is fixed internally at 3.8 V to 16.2 V. To convert the hexadecimal value to the voltage value, use the following steps: 1. Convert the hexadecimal value to decimal. For example, if the hexadecimal value is 0xA9, the decimal value is 169. 2. Calculate the voltage using the following equation: Voltage = 3.8 V + 12.4 V × Decimal Value/255 With a decimal value of 169, Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V LIMITER AND BATTERY TRACKING THRESHOLD CONTROL The SSM3582A contains an output limiter that can be used to limit the peak output voltage of the amplifier. The limiter works on the rms and peak value of the signal. The limiter threshold, slope, attack rate, and release rate are programmable using Register 0x0E, Register 0x0F, and Register 0x10 for the left channel and Register 0x11, Register 0x12, Register 0x13 for the right channel. The limiter can be enabled or disabled using LIM_EN_L, Bits[1:0] in Register 0x0E for the left channel and the LIM_EN_R bits, Bits[1:0] in Register 0x11, for the right channel. |
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