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SSM3582ACPZ-R7 数据表(PDF) 45 Page - Analog Devices

部件名 SSM3582ACPZ-R7
功能描述  2×, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier
PDF  58 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM3582ACPZ-R7 数据表(HTML) 45 Page - Analog Devices

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Data Sheet
SSM3582A
Rev. A | Page 45 of 58
Address: 0x0A, Reset: 0x07, Name: SAI_CTRL2
SDATA Edge Delay Mode.
1: Half cycle delay of SDATA.
0: Norm al operation.
Autom atic TDM Slot Selection.
1:
ADDRx pin s ettings .
Set TDM s lots autom atically us ing
0:
bits .
Set TDM s lots us ing TDM_SLOTx
Channel Volum e Link.
1: Link both channels to VOL_L control.
0:
controls .
Us e independent VOL_L and VOL_R
Audio Input Data Width.
1: 16 bits .
0: 24 bits .
High Frequency Clipper Link.
1:
bits .
Link both channels to DAC_CLIP_L
0:
bits .
Us e independent left and right DAC_CLIP_x
Volum e Control Zero-Cros s ing Detection.
1:
is detected (m ay be different per channel).
Only change volum e when zero-cros s ing
0: Allow volum e to change at all tim es .
0
1
1
1
2
1
3
0
4
0
5
0
6
0
7
0
[7] SDATA_EDGE (R/W)
[0] AUTO_SLOT (R/W)
[6:5] RESERVED
[1] VOL_LINK (R/W)
[4] DATA_WIDTH (R/W)
[2] CLIP_LINK (R/W)
[3] VOL_ZC_ONLY (R/W)
Table 34. Bit Descriptions for SAI_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
7
SDATA_EDGE
SDATA Edge Delay Mode.
0x0
R/W
0
Normal operation.
1
Half cycle delay of SDATA.
[6:5]
RESERVED
Reserved.
0x0
R
4
DATA_WIDTH
Audio Input Data Width.
0x0
R/W
0
24 bits.
1
16 bits.
3
VOL_ZC_ONLY
Volume Control Zero-Crossing Detection.
0x0
R/W
0
Allow volume to change at all times.
1
Only change volume when zero-crossing is detected (may be different per channel).
2
CLIP_LINK
High Frequency Clipper Link.
0x1
R/W
0
Use independent left and right DAC_CLIP_x bits.
1
Link both channels to DAC_CLIP_L bits.
1
VOL_LINK
Channel Volume Link.
0x1
R/W
0
Use independent VOL_L and VOL_R controls.
1
Link both channels to VOL_L control.
0
AUTO_SLOT
Automatic TDM Slot Selection.
0x1
R/W
0
Set TDM slots using TDM_SLOT_x bits.
1
Set TDM slots automatically using the ADDRx pin settings.
Address: 0x0B, Reset: 0x00, Name: SLOT_LEFT_CTRL
Left Channel Slot Selection.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED
[4:0] TDM_SLOT_L (R/W)
Table 35. Bit Descriptions for SLOT_LEFT_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
TDM_SLOT_L
Left Channel Slot Selection.
0x0
R/W



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