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RC19302A00AGNT#KD0 数据表(PDF) 28 Page - Renesas Technology Corp

部件名 RC19302A00AGNT#KD0
功能描述  PCIe Gen7 1.8V 2-Input Clock Mux Family with LOS
PDF  62 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RC19302A00AGNT#KD0 数据表(HTML) 28 Page - Renesas Technology Corp

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R31DS0210EU0106 Rev.1.06
Page 28
May 11, 2026
RC193xx Datasheet
2.4.9
SMBus Electrical Characteristics
Figure 9. SMBus Target Timing Diagram
Table 26. SMBus DC Electrical Characteristics [1]
1. VOH is governed by the VPUP, the voltage rail to which the pull-up resistors are connected. The maximum VPUP voltage is 3.6V.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
VIH
High-level Input Voltage for SCLK and SDATA
VDD = 1.8V
0.8 VDD
-
3.6
V
VIL
Low-level Input Voltage for SCLK and SDATA
VDD = 1.8V
-
-
0.3 VDD
VHYS
Hysteresis of Schmitt Trigger Inputs
-
0.05 VDD
-
-
VOL
Low-level Output Voltage for SCLK and SDATA
IOL = 4mA
-
0.28
0.4
IIN
Input Leakage Current per Pin
-
[2]
2. See I/O Electrical Characteristics.
-
[2]
µA
CB
Capacitive Load for Each Bus Line
-
-
-
400
pF
Table 27. SMBus AC Electrical Characteristics
Symbol
Parameter
Conditions
100kHz Class
Unit
Minimum Maximum
fSMB
SMBus Operating Frequency
[1]
1. Power must be applied and PWRGD_PWRDNb must be a 1 for the SMBus to be active.
10
100
kHz
tBUF
Bus free time between STOP and START Condition
-
4.7
-
µs
tHD:STA
Hold Time after (REPEATED) START Condition
[2]
4
-
μs
tSU:STA
REPEATED START Condition Setup Time
-
4.7
-
µs
tSU:STO
STOP Condition Setup Time
-
4
-
µs
tHD:DAT
Data Hold Time
[3]
0
-
ns
tSU:DAT
Data Setup Time
-
250
-
ns
tTIMEOUT Detect SCL_SCLK Low Timeout
[4]
25
35
ms
tTIMEOUT Detect SDA_nCS Low Timeout
[5]
25
35
ms
tLOW
Clock Low Period
-
4.7
-
µs
tHIGH
Clock High Period
[6]
4
50
µs
tLOW:SEXT
Cumulative Clock Low Extend Time
(target [slave] device)
[7]
N/A.
The RC193xx does not
extend the clock.
ms
tLOW:MEXT
Cumulative Clock Low Extend Time
(host [master] device)
[8]
N/A.
The RC193xx is not a
host device.
ms
tF
Clock/Data Fall Time
[9]
-
300
ns
tR
Clock/Data Rise Time
[9]
-
1000
ns
tSPIKE
Noise Spike Suppression Time
[10]
-
-
ns
s
tHD:STA
tLOW
tHIGH
tSU:STA
sr
tHD:STA
tSU:STO
tBUF
s
P
SCL
SDA
MSB
tSU:DAT
tHD:DAT



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