R31DS0210EU0106 Rev.1.06

Page 27

May 11, 2026

RC193xx Datasheet

IDDCLK_X

VDDCLK_X Operating Current

per Output Pair, 85Ω

impedance [4]

Fast slew rate, source-terminated load at

100MHz. PWRGD_PWRDNb = 1.

-

9.8

10.4

mA

Fast slew rate, double-terminated load at

100MHz. PWRGD_PWRDNb = 1.

-

11.5

12.1

Fast slew rate, source-terminated load at

maximum output frequency.

PWRGD_PWRDNb = 1.

-

12.4

12.8

Fast slew rate, double-terminated load at

maximum output frequency.

PWRGD_PWRDNb = 1.

-

15.0

15.4

IDDCLK_X

VDDCLK_X Operating Current

per Output Pair, 34Ω

impedance [4]

Fast slew rate, source-terminated load at

100MHz. PWRGD_PWRDNb = 1.

-

9.2

10.1

mA

Fast slew rate, double-terminated load at

100MHz. PWRGD_PWRDNb = 1.

-

14.5

15.5

Fast slew rate, source-terminated load at

maximum output frequency.

PWRGD_PWRDNb = 1.

-

15.4

16.3

Fast slew rate, double-terminated load at

maximum output frequency.

PWRGD_PWRDNb = 1.

-

21.2

21.6

Fast slew rate, receiver-terminated load at

maximum output frequency.

PWRGD_PWRDNb = 1.

-

21.2

21.6

IDDCLK_CORE_X

VDDCLK_X Core Operating

Current, per VDDCLK_X, all

Outputs Disabled

PWRGD_PWRDNb = 1, all outputs disabled,

CLKIN = 100MHz.

-

2.2

2.7

mA

PWRGD_PWRDNb = 1, all outputs disabled,

CLKIN = maximum operating frequency.

-

5.8

7.2

IDDINx

VDDINx Operating Current

Deselected input channel, per VDDIN pin.

PWRGD_PWRDNb = 1.

-

1.7

2.1

mA

Selected input channel, per VDDIN pin.

PWRGD_PWRDNb = 1.

-

11.1

14.3

mA

IDDDIG

VDDDIG Current

PWRGD_PWRDNb = 0 or 1.

-

0.12

0.18

mA

IDDA

VDDA Current

Core logic supply, independent of either bank.

PWRGD_PWRDNb = 0 or 1.

-

0.3

0.32

mA

IDDINxPD

VDDINX Power-down Current

per IDDINX pin.

PWRGD_PWRDNb = 0 (does not apply to

RC19302).

-

1.6

2.1

mA

IDDCLK_xPD

VDDCLK_x Power-down

Current per output bank [5]

PWRGD_PWRDNb = 0 (does not apply to

RC19302).

-

1.8

2

mA

1. See Test Loads.

2. Output voltage set to 800mV. Slew rate has negligible effect on current consumption, so only fast is listed.

3. Total operating current is obtained by adding (IDDCLK x number of outputs used) + IDDCLK_CORE_0 + IDDCLK_CORE_1 + IDDIN0 + IDDIN1 + IDDA +

IDDDIG. For example, let’s assume that the RC19308 is being used at 100MHz with 100ohm source terminated outputs and that only six outputs

are used. CLKIN1 is selected. The typical operating current would be IDDCLK x 6 + IDDCLK_CORE0 + IDDCLK_CORE0 + IDDIN0 + IDDIN1 + IDDA + IDDDIG

or (8.5 x 6)mA + 2.2mA + 2.2mA + 1.7mA + 11.1mA + 0.3mA + 0.14mA = 68.6mA typical. Note: VDDCLK_0 serves CLK[3:0]. VDDCLK_1 serves

CLK[7:4]. Total power down current is obtained by adding IDDCLK_0PD + IDDCLK_1PD + IDDIN0PD + IDDIN1PD + IDDDIG_PD + IDDA.

4.

The value specified is for one output pair. Multiply this value by the number of outputs in use.

5. On the RC19308, bank 0 is powered by 3 VDDCLK_0 pins and bank 1 is powered by 3 VDDCLK_1 pins. This value is the total current per output

bank, not per VDDCLK pin. This parameter needs to be counted only twice.

Table 25. Power Supply Current [1][2][3] (Cont.)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit