RC19302A00AGNT#KD0 datasheet(46/62 Pages) RENESAS

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R31DS0210EU0106 Rev.1.06

Page 46

May 11, 2026

RC193xx Datasheet

5.3

Differential CLK Output Configurations

5.3.1

Internal CLK Source Termination Enabled (ZOUT_SEL_tri = 0 or 1)

The RC193xx LP-HCSL CLK outputs have internal source terminations and directly drive industry-standard

HCSL-level inputs with no external components. They support both 85 and 100 ohm differential impedances

(ZO = ZDIF = 85 or 100 ohm) in Figure 17 through Figure 19. The combination of source termination and receiver

termination results in a double-terminated load. The CLK outputs can drive double-terminated loads, however,

when double-terminated, the CLK output swing will be half of the source-terminated values.

Figure 17. Direct-Coupled Source-Terminated HCSL (ZOUT_SEL_tri = 0 or 1)

Table 32. CLKIN Configuration Bits

Configuration

CLKIN1

AC_IN1

B35[3]

CLKIN1

RX_TERM1

B35[2]

CLKIN0

AC_IN0

B35[1]

CLKIN0

RX_TERM0

B35[0]

Notes

HCSL Input Levels (PCIe

Standard)

Default values

LVDS Input Levels

Eliminates need for external

bias circuit. Must use

external RT.

External AC-Coupling

Eliminates need for external

bias circuit.

Receiver Termination

Prevents reflections for non-

PCIe applications.

Figure 13. HCSL Input Levels (PCIe Standard)

Figure 14. LVDS Input Levels

Figure 15. External AC-Coupling

Figure 16. Receiver Termination

CLKIN

CLKINb

HCSL/LP-HCSL Inputs

Bias

CLKIN

CLKINb

LVDS

RT = 85 or 100 ohms

CAC

Bias

CLKIN

CLKINb

Externally AC-coupled

CLKIN

CLKINb

Internal receiver termination

RC193xx

HCSL

Input

ZDIF

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