STLS2F01 datasheet(7/48 Pages) STMICROELECTRONICS

7 / 48 page

STLS2F01

Introduction

7/48

The instruction pipeline allows to fetch and code four instructions per cycle and dynamically

issue the decoded instructions to five fully pipe lined function components.

The STLS2F01 uses out-of-order execution and aggressive memory hierarchy design to

maximize pipeline efficiency.

Out-of-order execution is accomplished with a combination of register renaming, dynamic

scheduling, and branch prediction techniques. The result is fewer pipeline stalls caused by

WAR (write after read) and WAW (write after write) hazards, RAW (read after write) hazards,

and control hazards. The STLS2F01 has a 64-entry physical register file for fixed- and

floating-point register renaming, a 16-entry fixed-point reservation station, and a 16-entry

floating-point reservation station that is responsible for out-of-order instruction issuing. A 64-

entry ROQ (reorder queue) ensures that out-of-order executed instructions are committed in

the program order. For precise branch prediction, a 16-entry branch target buffer (BTB), a

4K-entry branch history table (BHT), a 9-bit global history register (GHR), and a 4-entry

return address stack (RAS) are used to record branch history information.

The STLS2F01 memory hierarchy is also engineered for high performance. There is a

64 Kbyte instruction cache, a 64 Kbyte data cache, and a 512 Kbyte level-two cache. All

four-way set associative. The on-chip DDR memory allows the STLS2F01 to achieve high

memory bandwidth with low latency. The fully associative translation lookaside buffer (TLB)

has 64 entries, each mapping an odd and even page. A 24-entry memory access queue

contains a content-addressable memory for dynamic memory disambiguation and allows

the STLS2F01 to implement out-of-order memory access, non-blocking cache, load

speculation, and store forwarding.

The STLS2F01 has two fixed-point functional units, two floating-point functional units, and

one memory access unit. The floating-point units can also execute 32- or 64-bit fixed-point

instructions and 8- or 16-bit SIMD fixed-point instructions through extension of the fmt field

of the floating-point instructions. The SIMD unit extends the STLS2E02 with new XX SSE2

type instructions.

The basic pipeline stages of the STLS2F01 include instruction fetch, pre-decode, decode,

The STLS2F01 device is manufactured in ST 90 nm CMOS technology.

The STLS2F01 is an evolution of the STLS2E02 with enhanced I/O and memory accessing

bandwidth and a software working frequency changing scheme.

The STLS2F01 has a standard 32-bit PCI/PCI-X interface, a standard 64-bit DDR2

interface, an 8/16-bit local I/O interface, a 4-bit GPIO interface.

The STLS2F01 achieves a higher memory access bandwidth by utilizing a 64-bit DDR2

memory controller.

Compared to its predecessor, the STLS2F01 provides better power management ability by

using a software manageable working frequency changing scheme. The operating system

can utilize this feature to change the processor frequency according to the workload.

The STLS2F01 integrates a video accelerate module in its write data path to the PCI/PCI-X

controller. Coupled with software drivers, the video accelerate module can transfer YUV

format video data to RGB format and zoom automatically. This greatly reduces the

processor's workload when the system utilizes a simple VGA controller.

The cores are centered on 2x2 AXI cross bar with 128-bit width data bus. The CPU core and

PCI/PCI-X slave takes up two master ports, DDR2 controller one slave port, and all other

modules including the PCI/PCI-X master share one slave port.

STLS2F01 数据表(PDF) 7 Page - STMicroelectronics

STLS2F01 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载