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STLS2F01 数据表(PDF) 29 Page - STMicroelectronics |
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STLS2F01 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 48 page  STLS2F01 DDR2 SDRAM controller interface description 29/48 DLL_DQS_DELAY_1 54:48 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 1 during reads. DLL_DQS_DELAY_0 46:40 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 0 during reads. COMMAND_AGE_COUNT 37:32 0x0 0x0-0x3f Initial value of individual command aging counters for command aging. CONF_CTL_11[31:0] Offset: 0xb0 DDR2 667:0x1d1d1d1d DLL_DQS_DELAY_6 30:24 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 6 during reads. DLL_DQS_DELAY_5 22:16 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 5 during reads. DLL_DQS_DELAY_4 14:8 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 4 during reads. DLL_DQS_DELAY_3 6:0 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 3 during reads. CONF_CTL_11[63:32] Offset: 0xb0 DDR2 667:0x507f1d1d WR_DQS_SHIFT 62:56 0x0 0x0-0x7f Fraction of a cycle to delay the clk_wr signal in the controller. DQS_OUT_SHIFT 54:48 0x0 0x0-0x7f Fraction of a cycle to delay the write DQS signal to the DRAMs during writes. DLL_DQS_DELAY_8 46:40 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 8 during reads. DLL_DQS_DELAY_7 38:32 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 7 during reads. CONF_CTL_12[31:0] Offset: 0xc0 DDR2 667:0x0e000000 TRAS_MIN 31:24 0x0 0x0-0xff DRAM TRAS_MIN parameter in cycles. OUT_OF_RANGE_LENGTH 23:16 0x0 0x0-0xff Length of command that caused an Out-of-Range interrupt. Read-only. ECC_U_SYND 15:8 0x0 0x0-0xff Syndrome for uncorrectable ECC event. Read-only. ECC_C_SYND 7:0 0x0 0x0-0xff Syndrome for correctable ECC event. Read-only. CONF_CTL_12[63:32] Offset: 0xc0 DDR2 667:0x002a3305 Table 12. DDR SDRAM configuration parameter register format (continued) Parameters Bits Default value Range Description |
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