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STLS2F01 数据表(PDF) 32 Page - STMicroelectronics

部件名 STLS2F01
功能描述  Loongson 2F: High performance 64-bit superscalar MIPS® microprocessor
PDF  48 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLS2F01 数据表(HTML) 32 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F01
32/48
EMRS3_DATA
46:32 0x0000
0x0-
0x7fff
EMRS3 data.
CONF_CTL_19[31:0]
Offset: 0x130
DDR2 667:0x00c8006b
TDLL
31:16 0x0000 0x0-0xffff DRAM TDLL parameter in cycles.
TCPD
15:0
0x0000 0x0-0xffff DRAM TCPD parameter in cycles.
CONF_CTL_19[63:32]
Offset: 0x130
DDR2 667:0x48e10002
TRAS_MAX
63:48 0x0000 0x0-0xffff
DRAM TRAS_MAX parameter in
cycles.
TPDEX
47:32 0x0000 0x0-0xffff DRAM TPDEX parameter in cycles.
CONF_CTL_20[31:0]
Offset: 0x140
DDR2 667:0x00c8002f
TXSR
31:16 0x0000 0x0-0xffff DRAM TXSR parameter in cycles.
TXSNR
15:0
0x0000 0x0-0xffff DRAM TXSNR parameter in cycles.
CONF_CTL_20[63:32]
Offset: 0x140
DDR2 667:0x00000000
XOR_CHECK_BITS
63:48 0x0000 0x0-0xffff
Value to XOR with generated ECC
codes for forced write check.
VERSION
47:32 0x2041
0x2041
Controller version number. Read-
only.
CONF_CTL_21[31:0]
Offset: 0x150
DDR2 667:0x00000036
ECC_C_ADDR[7:0]
31:24 0x0000
0x0-
0x1ffffffff
Address of correctable ECC event.
Read-only.
TINIT
23:0
0x0000
0x0-
0xfffff
DRAM TINIT parameter in cycles.
CONF_CTL_21[63:32]
Offset: 0x150
DDR2 667:0x00000000
ECC_C_ADDR[36:8]
60:32
0x0
0x0-
0x1ffffffff
Address of correctable ECC event.
Read-only.
CONF_CTL_22[31:0]
Offset: 0x160
DDR2 667:0x00000000
ECC_U_ADDR[31:0]
31:0
0x0
0x0-
0x1ffffffff
Address of uncorrectable ECC event.
Read-only.
CONF_CTL_22[63:32]
Offset: 0x160
DDR2 667:0x00000000
ECC_U_ADDR[36:32]
36:32
0x0
0x0-
0x1ffffffff
Address of uncorrectable ECC event.
Read-only.
CONF_CTL_23[31:0]
Offset: 0x170
DDR2 667:0x00000000
OUT_OF_RANGE_ADDR[31:0]
31:0
0x0
0x0-
0x1ffffffff
Address of command that caused an
Out-of-Range interrupt. Read-only
CONF_CTL_23[63:32]
Offset: 0x170
DDR2 667:0x00000000
OUT_OF_RANGE_ADDR[36:32] 36:32
0x0
0x0-
0x1ffffffff
Address of command that caused an
Out-of-Range interrupt. Read-only.
CONF_CTL_24[31:0]
Offset: 0x180
DDR2 667:0x00000000
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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