STLS2F01 datasheet(23/48 Pages) STMICROELECTRONICS

23 / 48 page

STLS2F01

DDR2 SDRAM controller interface description

23/48

4.4

DDR2 SDRAM parameter format

Since different DDR2 SDRAMs may be used in the system, DDR2 SDRAM needs

configuration after power-on reset. The JESD79-2B standard defines detailed configuration

operation and process. DDR2 is not available before the memory is initialized. Memory

initialization sequence:

System reset, aresetn signal is set 0, all registers content will be initial value.

System reset release, aresetn signal is set 1.

Issue 64-bit write command to configuration register, all 29 registers are configured. If

Issue 64-bit write command to register CTRL_03. Set the parameter of start to 1. Then,

memory controller will send initial instruction to memory automatically.

In the STLS2F01 processor design, after the system motherboard is initialized, the DDR2

SDRAM controller needs configure memory type before the memory is used. Specifically,

corresponding configuration parameters are written into the 29 64-bit registers

corresponding to the physical address 0x0000 0000 0FFF FE00. In one register, one,

multiple or partial parameter data can be included. The configuration register and its

parameters are shown in Table 12 Note: the bits not used are all reserved bits.

Table 12.

DDR SDRAM configuration parameter register format

Parameters

Bits

Default

value

Range

Description

CONF_CTL_00[31:0] Offset: 0x00

DDR2 667:0x00000101

AREFRESH

24:24

0x0

0x0-0x1

Initiate auto-refresh when specified

by AUTO_REFRESH_MODE. Write-

only

16:16

0x0

0x0-0x1

Enable auto pre-charge mode of

controller.

ADDR_CMP_EN

8:8

0x0

0x0-0x1

Enable address collision detection

for command queue placement logic.

ACTIVE_AGING

0:0

0x0

0x0-0x1

Enable command aging in the

command queue, avoiding low

priority command hungry.

CONF_CTL_00[63:32] Offset: 0x00

DDR2 667:0x01000100

DDR2_SDRAM_MODE

56:56

0x0

0x0-0x1

DDRI or DDRII mode.

CONCURRENTAP

48:48

0x0

0x0-0x1

Allow controller to issue command to

other banks while a bank is in auto

pre-charge. Note: most DDR2 DIMM

vendor do not support this feature.

BANK_SPLIT_EN

40:40

0x0

0x0-0x1

Enable bank splitting for command

queue placement logic.

AUTO_REFRESH_MODE

32:32

0x0

0x0-0x1

Sets if auto-refresh will be at next

burst or next command boundary.

CONF_CTL_01[31:0] Offset: 0x10

DDR2 667:0x00010000

STLS2F01 数据表(PDF) 23 Page - STMicroelectronics

STLS2F01 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载

链接网址

STLS2F01 数据表(PDF) 23 Page - STMicroelectronics

STLS2F01 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表 下载

链接网址

数据表下载