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STLS2F01 数据表(PDF) 26 Page - STMicroelectronics

部件名 STLS2F01
功能描述  Loongson 2F: High performance 64-bit superscalar MIPS® microprocessor
PDF  48 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLS2F01 数据表(HTML) 26 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F01
26/48
AXI0_R_PRIORITY
33:32
0x0
0x0-0x3
Priority of read command from port 0.
CONF_CTL_05[31:0]
Offset: 0x50
DDR2 667:0x04050202
COLUMN_SIZE
26:24
0x0
0x0-0x7
Difference between number of
column pins available and number
being used.
CASLAT
18:16
0x0
0x0-0x7
Encoded CAS latency sent to
DRAMs during initialization.
ADDR_PINS
10:8
0x0
0x0-0x7
Difference between number of
address pins available and number
being used.
RTT_PAD_TERMINATION
1:0
0x0
0x0-0x3
Set termination resistance in
controller pads.
CONF_CTL_05[63:32]
Offset: 0x50
DDR2 667:0x00000000
Q_FULLNESS
58:56
0x0
0x0-0x7
Quantity that determines command
queue full.
PORT_DATA
_ERROR_TYPE
50:48
0x0
0x0-0x7
Type of error and access type that
caused the PORT data error. Read-
only.
bit 0 – data overflow. The write data
quantity exceeded the
Maximum_Byte_Request configured
option.
bit 1 – write data interleaved beyond
supported interleaving depth.
bit 2 – ECC 2-bit error.
OUT_OF_RANGE_TYPE
42:40
0x0
0x0-0x7
Type of command that caused and
Out-of-Range interrupt. Read-only.
MAX_CS_REG
34:32
0x4
0x0-0x4
Maximum number of chip selects
available. Read-only
CONF_CTL_06[31:0]
Offset: 0x60
DDR2 667:0x03040203
TRTP
26:24
0x0
0x0-0x7
DRAM TRTP parameter in cycles.
TRRD
18:16
0x0
0x0-0x7
DRAM TRRD parameter in cycles.
TEMRS
10:8
0x0
0x0-0x7
DRAM TEMRS parameter in cycles.
TCKE
2:0
0x0
0x0-0x7
Minimum CKE pulse width.
CONF_CTL_06[63:32]
Offset: 0x60
DDR2 667:0x0a040305
APREBIT
59:56
0x0
0x0-0xf
Location of the auto pre-charge bit in
the DRAM address.
WRLAT
50:48
0x0
0x0-0x7
DRAM WRLAT parameter in cycles.
TWTR
42:40
0x0
0x0-0x7
DRAM TWTR parameter in cycles.
TWR_INT
34:32
0x0
0x0-0x7
DRAM TWR parameter in cycles.
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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