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STLS2F01 数据表(PDF) 25 Page - STMicroelectronics

部件名 STLS2F01
功能描述  Loongson 2F: High performance 64-bit superscalar MIPS® microprocessor
PDF  48 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLS2F01 数据表(HTML) 25 Page - STMicroelectronics

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STLS2F01
DDR2 SDRAM controller interface description
25/48
CONF_CTL_03[31:0]
Offset: 0x30
DDR2 667:0x01000000
RW_SAME_EN
24:24
0x0
0x0-0x1
Enable read/write grouping for
command queue placement logic.
REG_DIMM_EN
16:16
0x0
0x0-0x1
Enable registered DIMM operation of
the controller.
REDUC
8:8
0x0
0x0-0x1
Enable the half data path (32-bit)
feature of the controller.
PWRUP_SREFRESH_EXIT
0:0
0x0
0x0-0x1
Power-up via self-refresh instead of
full memory initialization.
CONF_CTL_03[63:32]
Offset: 0x30
DDR2 667:0x01010000
SWAP_PORT_RW_SAME_EN
56:56
0x0
0x0-0x1
Enable command swapping logic
between commands of the same
type from the same port in execution
unit.
SWAP_EN
48:48
0x0
0x0-0x1
Enable command swapping logic in
execution unit.
START
40:40
0x0
0x0-0x1
Initiate command processing in the
controller.
SREFRESH
32:32
0x0
0x0-0x1
Place DRAMs in self-refresh mode.
CONF_CTL_04[31:0]
Offset: 0x40
DDR2 667:0x00010101
WRITE_MODEREG
24:24
0x0
0x0-0x1
Write EMRS data to the DRAMs.
Write-only.
WRITEINTERP
16:16
0x0
0x0-0x1
Allow controller to interrupt write
bursts to the DRAMs with a read
command.
TREF_ENABLE
8:8
0x0
0x0-0x1
Issue self-refresh commands to the
DRAMs every TREF cycle.
TRAS_LOCKOUT
0:0
0x0
0x0-0x1
Allow the controller to execute auto
pre-charge commands before
TRAS_MIN expires.
CONF_CTL_04[63:32]
Offset: 0x40
DDR2 667:0x01000202
RTT_0
57:56
0x0
0x0-0x3
On-Die termination resistance
setting for all DRAM devices.
CTRL_RAW
49:48
0x0
0x0-0x3
ECC error checking and correcting
control.
2’b00 – no ECC
2’b01 – report error only, not
corrected
2’b10 – no ECC device used
2’b11 – report and correct ECC error
AXI0_W_PRIORITY
41:40
0x0
0x0-0x3
Priority of write command from port 0.
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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