STLS2F01 datasheet(21/48 Pages) STMICROELECTRONICS

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STLS2F01

DDR2 SDRAM controller interface description

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DDR2 SDRAM controller interface description

The STLS2F01 integrates a built-in memory controller compliant with DDR2 SDRAM

standard (JESD79-2B). The STLS2F01 provide JESD79-2B-compliant read/write

operations onto memory.

4.1

DDR2 SDRAM controller features

The STLS2F01 CPU supports up to 4 physical memory by using two DDR SDRAM chip

select signals, with a 18-bit address bus (15-bit row/column address and 3-bit logic bank

bus). The maximum address space is 128GB (237 bytes).

This device supports all the JESD79-2B-compatible memory chips. The DDR2 controller

parameters can be set to support specific memory chip type. The maximum number of chip

selection (CS_n) is 2-bit. The maximum width of row address (RAS_n) is 15-bit, and the

maximum width of column address (CAS_n) is 14-bit. And there is 3-bit logic bank bus

(BANK_n).

For example, in the 4GB address space configuration of 2-bit CS_n, 3-bit BANK_n, 12-bit

RAS_n and 12-bit CAS_n, the physical memory address CPU required can be translated

into row/column address as shown in the DDR2 SDRAM row/column address translation

paragraph.

DDR2 SDRAM row/column address translation

The built-in memory controller IC receives only memory read/write requests from a

processor or external device. The controller IC is in Slave state whenever memory are read

or written.

A dynamic page management policy is implemented on the integrated memory controller.

For one access to memory, the controller selects Open Page/Close Page strategies on a

hardware circuit, without software designers’ intervention. The memory controller features:

●

Full pipeline support to command and read/write data of interface

●

Increasing bandwidth by merging and sorting memory command

●

Modify fundamental parameters through the configuration of register read/write ports

●

Built-in delay compensation circuit (DCC), it is used to send/receive data reliably

●

1-bit and 2-bit error detection, 1-bit error correction by error correcting-code (ECC)

●

Frequency: 133 MHz - 333 MHz

4.2

DDR2 SDRAM read protocol

As showed in Figure 7 DDR2 SDRAM read protocol, the command (CMD) includes RAS_n,

CAS_n and WE_n. When a read request happens, RAS_n=1,CAS_n=0,and WE_n=1.

32 31

30 29

18 17

15 14

3 2

CS_n

RAS_n

BANK_n

CAS_n

Byte_enable

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