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STLS2F01 数据表(PDF) 24 Page - STMicroelectronics

部件名 STLS2F01
功能描述  Loongson 2F: High performance 64-bit superscalar MIPS® microprocessor
PDF  48 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLS2F01 数据表(HTML) 24 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F01
24/48
ECC_DISABLE_W_UC_ERR
24:24
0x0
0x0-0x1
Disable auto-corruption of ECC
when un-correctable errors occur in
R/M/W operations.
DQS_N_EN
16:16
0x0
0x0-0x1
Single-ended or differential DQS
pins.
DLL_BYPASS_MODE
8:8
0x0
0x0-0x1
Enable the DLL bypass feature of the
controller.
DLLLOCKREG
0:0
0x0
0x0-0x1
Status of DLL lock coming out of
master delay. Read-only.
CONF_CTL_01[63:32] Offset: 0x10
DDR2 667:0x00100000
FWC
56:56
0x0
0x0-0x1
Force a write checks. Xor
XOR_CHECK_BITS with ECC code
and write to memory. Write-only
FAST_WRITE
48:48
0x0
0x0-0x1
Sets when write command are
issued to DRAM device.
ENABLE_QUICK_SREFRESH
40:40
0x0
0x0-0x1
Allows user to interrupt memory
initialization to enter self-refresh
mode.
EIGHT_BANK_MODE
32:32
0x0
0x0-0x1
Number of banks on the DRAM(s).
CONF_CTL_02[31:0] Offset: 0x20
DDR2 667:0x00000000
NO_CMD_INIT
24:24
0x0
0x0-0x1
Disable DRAM command until TDLL
has expired during initialization.
INTRPTWRITENA
16:16
0x0
0x0-0x1
Allow the controller to interrupt a
combined write command with auto
pre-charge with another write
command.
INTRPTREADA
8:8
0x0
0x0-0x1
Allow the controller to interrupt a
combined read with auto pre-charge
command with another read
command.
INTRPTAPBURST
0:0
0x0
0x0-0x1
Allow the controller to interrupt an
auto pre-charge command with
another command.
CONF_CTL_02[63:32]
Offset: 0x20
DDR2 667:0x01000101
PRIORITY_EN
56:56
0x0
0x0-0x1
Enable priority for command queue
placement logic.
POWER_DOWN
48:48
0x0
0x0-0x1
Disable clock enable and set DRAMs
in power-down state.
PLACEMENT_EN
40:40
0x0
0x0-0x1
Enable placement logic for command
queue.
ODT_ADD_TURN_CLK_EN
32:32
0x0
0x0-0x1
Enable extra turn-around clock
between back-to-back reads/writes
to different chip selects.
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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