STLS2F01 datasheet(31/48 Pages) STMICROELECTRONICS

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STLS2F01

DDR2 SDRAM controller interface description

31/48

DLL_LOCK

24:16

0x0

0x0-0x1ff

Number of delay elements in master

DLL lock. Read-only

DLL_INCREMENT

8:0

0x0

0x0-0x1ff

Number of elements to add to

DLL_START_POINT when searching

for lock.

CONF_CTL_15[63:32]

Offset: 0xf0

DDR2 667:0x00b4000a

DQS_OUT_SHIFT_BYPASS

56:48

0x0

0x0-0x1ff

Number of delay elements to include

in the write DQS signal to the

DRAMs during writes when DLL is

being bypassed.

DLL_START_POINT

40:32

0x0

0x0-0x1ff

Initial delay count when searching for

lock in master DLL.

CONF_CTL_16[31:0]

Offset: 0x100

DDR2 667:0x00000087

INT_ACK

25:16

0x0

0x0-0x3ff

Clear mask of the INT_STATUS

parameter. Write-only.

WR_DQS_SHIFT_BYPASS

8:0

0x0

0x0-0x1ff

Number of delay elements to include

in the clk_wr signal in the controller

when DLL is being bypassed.

CONF_CTL_16[63:32]

Offset: 0x100

DDR2 667:0x00000000

INT_STATUS

58:48

0x0

0x0-0x7ff

Status of interrupt features in the

controller. Read-only.

INT_MASK

42:32

0x0

0x0-0x7ff

Mask for controller_int signals from

the INT_STATUS parameter.

CONF_CTL_17[31:0]

Offset: 0x110

DDR2 667:0x0000181b

EMRS1_DATA

30:16

0x0

0x0-0x7ff EMRS1 data.

TREF

13:0

0x0

0x0-0x3ff DRAM TREF parameter in cycles.

CONF_CTL_17[63:32]

Offset: 0x110

DDR2 667:0x00000000

EMRS2_DATA_1

62:48 0x0000

0x0-

0x7fff

EMRS2 data for chip select 1.

EMRS2_DATA_0

46:32 0x0000

0x0-

0x7fff

EMRS2 data for chip select 0.

CONF_CTL_18[31:0]

Offset: 0x120

DDR2 667:0x00000000

EMRS2_DATA_3

30:16 0x0000

0x0-

0x7fff

EMRS2 data for chip select 3.

EMRS2_DATA_2

14:0

0x0000

0x0-

0x7fff

EMRS2 data for chip select 2.

CONF_CTL_18[63:32]

Offset: 0x120

DDR2 667:0x001c0000

AXI0_EN_SIZE_LT_WIDTH_IN

STR

63:48 0x0000 0x0-0xffff

Allow narrow instructions from port 0

requestors with bit enabled.

Table 12.

DDR SDRAM configuration parameter register format (continued)

Parameters

Bits

Default

value

Range

Description

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