STLS2F01 datasheet(12/48 Pages) STMICROELECTRONICS

12 / 48 page

Interface description

STLS2F01

12/48

2.5

Initialization signals

Table 5 provides the names, definitions, and directions and descriptions of the initialization

signals.

The STLS2F01 processor includes two reset signals: SYSRESETn and PCI_RESETn.

●

SYSRESETn: This reset signal is the only way to reset whole STLS2F01 processor.

SYSCLK and MEMCLK must provide stable clock when SYSRESETn is valid. The

width of SYSRESETn should be more than one clock period. Internal reset-control

begins to reset internal logic when reset signal is invalid. The internal reset will be

finished after 64K SYSCLK cycle. Then reset exception vector could be executed

●

PCI_RESETn: This signal works as output when the processor works as a system

main bridge. And the reset of PCI-X devices in the system must be controlled by the

signal. When the processor works as PCI/PCI-X devices used in other system, the

signal works as input to reset the PCI interface of processor. (Note: Resetting PCI

interface when process is running may cause the processor stop working)

PCI_CONFIG: defines the mode of working of the processor interface. It must keep stable

during system reset, so that software could read this value from internal register after

system started. The PCI address of the first instruction is 0x1fc00000 when system starting

from PCI is configured. Otherwise the first instruction will be fetched from address 0 of Local

Bus ROM.

Table 5.

Initialization interface signals

Name

Input/output

Description

SYSRESETn

System reset. Low state of the signal must be maintained

more than one SYSCLK period. It can be asynchronous

to SYSCLK.

PCI_RESETn

I/O

PCI interface reset.

PCI_CONFIG

PCI Configuration

undefined

6:5 PCI-X bus speed selection

4 PCI-X bus mode

Master mode

Start from PCI

External PCI arbitration

16-bit starting ROM

Note:

PCI-X BUS mode

PCI 33/66

PCI-X 66

PCI-X 100

PCI-X 133

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