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STLS2F01 数据表(PDF) 28 Page - STMicroelectronics |
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STLS2F01 数据表(HTML) 28 Page - STMicroelectronics |
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28 / 48 page  DDR2 SDRAM controller interface description STLS2F01 28/48 ODT_WR_MAP_CS2 51:48 0x0 0x0-0xf ODT chip select 2 map for writes. Determines which chip(s) will have termination when a write occurs on chip 2. ODT_WR_MAP_CS1 43:40 0x0 0x0-0xf ODT chip select 1 map for writes. Determines which chip(s) will have termination when a write occurs on chip 1. ODT_WR_MAP_CS0 35:32 0x0 0x0-0xf ODT chip select 0 map for writes. Determines which chip(s) will have termination when a write occurs on chip 0. CONF_CTL_09[31:0] Offset: 0x90 DDR2 667:0x00000000 PORT_DATA_ERROR_ID 27:24 0x0 0x0-0xf Port number of command that caused the PORT data error. Read- only PORT_CMD_ERROR_TYPE 19:16 0x0 0x0-0xf Type of error and access type that caused the PORT command error. Read-only) PORT_CMD_ERROR_ID 11:8 0x0 0x0-0xf Port number of command that caused the PORT command error. Read-only OUT_OF_RANGE_SOURCE_I D 3:0 0x0 0x0-0xf Source ID of command that caused an Out-of-Range interrupt. Read- only CONF_CTL_09[63:32] Offset: 0x90 DDR2 667:0x0000050b OCD_ADJUST_PUP_CS0 60:56 0x0 0x0-0x1f OCD pull-up adjust setting for DRAMs for chip select 0. OCD_ADJUST_PDN_CS0 52:48 0x0 0x0-0x1f OCD pull-down adjust setting for DRAMs for chip select 0. TRP 43:40 0x0 0x0-0xf DRAM TRP parameter in cycles. TDAL 35:32 0x0 0x0-0xf DRAM TDAL parameter in cycles. CONF_CTL_10[31:0] Offset: 0xa0 DDR2 667:0x3f130200 AGE_COUNT 29:24 0x0 0x0-0x3f Initial value of master aging-rate counter for command aging. TRC 20:16 0x0 0x0-0x1f DRAM TRC parameter in cycles. TMRD 12:8 0x0 0x0-0x1f DRAM TMRD parameter in cycles. TFAW 4:0 0x0 0x0-0x1f DRAM TFAW parameter in cycles. CONF_CTL_10[63:32] Offset: 0xa0 DDR2 667:0x1d1d1d3f DLL_DQS_DELAY_2 62:56 0x0 0x0-0x7f Fraction of a cycle to delay the DQS signal from the DRAMs for dll_rd_dqs_slice 2 during reads. Table 12. DDR SDRAM configuration parameter register format (continued) Parameters Bits Default value Range Description |
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