STLS2F01 datasheet(17/48 Pages) STMICROELECTRONICS

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STLS2F01

I/O bus interface description

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I/O bus interface description

The STLS2F01 processor I/O interface consists of PCI bus and Local bus. PCI bus is used

to for generic peripheral devices interface, while Local bus is the simple interface to boot or

debug the processor.

3.1

PCI interface characteristic

The PCI interface features:

●

PCI 2.3 and PCI-X 1.0 compatible

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Support PCI 66 MHz and PCI-X133 MHz

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Support dual address cycle for 64-bit addressing

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Support 8 outstanding master request in PCI-X mode

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Support 4 delay-split read request in PCI-X mode

3.2

Host and agent mode

The STLS2F01’s PCI interface could be worked in Host mode or Agent mode. It depends on

initial signal PCI_CONFIG. When the processor works in Host mode, the interface initializes

the bus device according to the value of PCI_CONFIG[6:4]. In this case, PCI_IDSEL could

connect to GND directly. When the processor works in Agent mode, the initial value of PCI

bus defines the work-mode of the interface. In Host mode, on the system main board, the

value of PCI_CONFIG[6:4] should be set according to the ability of bus device. (Please refer

to PCI-X 1.0 standard)

3.3

PCI bus arbitrator

PCI/PCI-X bus arbitrator built in STLS2F01 supports 7 external masters at most. The

arbitration rules are two levels Round Robin scheduling. The level of each request is

determined by software configuration. The bus is granted to insert a dummy cycle during

switching. Bus parking can be configured as the last master or any specified master.

The internal request/grant wire of interface could be set to connect to the number 0

request/grant wire by PCI_CONFIG [1], so that the external bus arbitrator can be used.

3.4

System interface connection

The STLS2F01 processor can be easily implemented in uniprocessor system. Since no

multi-processor cache coherence protocol is supported in PCI interface, the cache

coherence should be managed by software in multiprocessor system.

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Single processor system connection

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