STLS2F01 datasheet(27/48 Pages) STMICROELECTRONICS

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STLS2F01

DDR2 SDRAM controller interface description

27/48

CONF_CTL_07[31:0]

Offset: 0x70

DDR2 667:0x000f090a

ECC_C_ID

27:24

0x0

0x0-0xf

Source ID associated with

correctable ECC event. Read-only

CS_MAP

19:16

0x0

0x0-0xf

Number of active chip selects used

in address decoding.

CASLAT_LIN_GATE

11:8

0x0

0x0-0xf

Adjusts data capture gate open by

half cycles.

CASLAT_LIN

3:0

0x0

0x0-0xf

Sets latency from read command

send to data receive from/to

controller.

CONF_CTL_07[63:32]

Offset: 0x70

DDR2 667:0x00000400

MAX_ROW_REG

59:56

0xf

0x0-0xf

Maximum width of memory address

bus. Read-only

MAX_COL_REG

51:48

0xe

0x0-0xe

Maximum width of column address in

DRAMs. Read-only

INITAREF

43:40

0x0

0x0-0xf

Number of auto-refresh command to

execute during DRAM initialization.

ECC_U_ID

35:32

0x0

0x0-0xf

Source ID associated with the

uncorrectable ECC even. Read-only.

CONF_CTL_08[31:0]

Offset: 0x80

DDR2 667:0x01020408

ODT_RD_MAP_CS3

27:24

0x0

0x0-0xf

ODT chip select 3 map for reads.

Determines which chip(s) will have

termination when a read occurs on

chip 3.

ODT_RD_MAP_CS2

19:16

0x0

0x0-0xf

ODT chip select 2 map for reads.

Determines which chip(s) will have

termination when a read occurs on

chip 2.

ODT_RD_MAP_CS1

11:8

0x0

0x0-0xf

ODT chip select 1 map for reads.

Determines which chip(s) will have

termination when a read occurs on

chip 1.

ODT_RD_MAP_CS0

3:0

0x0

0x0-0xf

ODT chip select 0 map for reads.

Determines which chip(s) will have

termination when a read occurs on

chip 0.

CONF_CTL_08[63:32]

Offset: 0x80

DDR2 667:0x01020408

ODT_WR_MAP_CS3

59:56

0x0

0x0-0xf

ODT chip select 3 map for writes.

Determines which chip(s) will have

termination when a write occurs on

chip 3.

Table 12.

DDR SDRAM configuration parameter register format (continued)

Parameters

Bits

Default

value

Range

Description

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