STLS2F01 datasheet(34/48 Pages) STMICROELECTRONICS

34 / 48 page

DDR2 SDRAM controller interface description

STLS2F01

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operation returns. In general, It is equal to or less than half period of ACALAT_LIN. The

Value of CASLAT_LIN is twice of the one of CAS.

CONF_CTL_15 DLL_INCREMENT

The parameter should not be set 0.

CONF_CTL_15 DLL_START_POINT

The parameter should not be set 0/1 and should be less than the 1.5 times of

DLL_LOCK_VALUE.

CONF_CTL_28 UB_DIMM

The parameter should be set 1, when unbuffered DIMM(s) are used. It should be set 0,

when the SDRAM(s) are used.

4.5

DDR2 SDRAM sample mode configuration

DDR2 SDRAM controller is integrated in the STLS2F01. And the delay compensation circuit

(using DLL) is used to sample return data of DQS. Since there is the delay of data return

path between the memory controller and SDRAM module, it is necessary to introduce a set

of control signals used to measure the delay.

The control signals of DDR2_GATE_I[3:0] and DDR2_GATE_O[3:0] are used to the delay

measurement. On the PCB, DDR2_GATE_I and DDR2_GAT_O are connected together to

imitate the wiring delay on the PCB. Thus, the accuracy of sampling can be guaranteed.

STLS2F01 数据表(PDF) 34 Page - STMicroelectronics