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STLS2F02 数据表(PDF) 30 Page - STMicroelectronics |
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STLS2F02 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 49 page  DDR2 SDRAM controller interface description STLS2F02 30/49 TRP 43:40 0x0 0x0-0xF DRAM TRP parameter in cycles. TDAL 35:32 0x0 0x0-0xF DRAM TDAL parameter in cycles. CONF_CTL_10[31:0] Offset: 0xA0 DDR2 667:0x3F130200 AGE_COUNT 29:24 0x0 0x0-0x3F Initial value of master aging-rate counter for cmd aging. TRC 20:16 0x0 0x0-0x1F DRAM TRC parameter in cycles. TMRD 12:8 0x0 0x0-0x1F DRAM TMRD parameter in cycles. TFAW 4:0 0x0 0x0-0x1F DRAM TFAW parameter in cycles. CONF_CTL_10[63:32] Offset: 0xA0 DDR2 667:0x1D1D1D3F DLL_DQS_DELAY_2 62:56 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 2 during reads. DLL_DQS_DELAY_1 54:48 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 1 during reads. DLL_DQS_DELAY_0 46:40 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 0 during reads. COMMAND_AGE_COUNT 37:32 0x0 0x0-0x3F Initial value of individual cmd aging counters for cmd aging. CONF_CTL_11[31:0] Offset: 0xB0 DDR2 667:0x1D1D1D1D DLL_DQS_DELAY_6 30:24 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 6 during reads. DLL_DQS_DELAY_5 22:16 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 5 during reads. DLL_DQS_DELAY_4 14:8 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 4 during reads. DLL_DQS_DELAY_3 6:0 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 3 during reads. CONF_CTL_11[63:32] Offset: 0xB0 DDR2 667:0x507F1D1D WR_DQS_SHIFT 62:56 0x0 0x0-0x7F Fraction of a cycle to delay the clk_wr signal in the controller. DQS_OUT_SHIFT 54:48 0x0 0x0-0x7F Fraction of a cycle to delay the write dqs signal to the DRAMs during writes. DLL_DQS_DELAY_8 46:40 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 8 during reads. Table 12. DDR SDRAM configuration parameter register format (continued) Parameters Bits Default value Range Description |
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