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STLS2F02 数据表(PDF) 35 Page - STMicroelectronics |
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STLS2F02 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 49 page ![]() STLS2F02 DDR2 SDRAM controller interface description 35/49 CONF_CTL_27[63:32] Offset: 0x1B0 DDR2 667:0x00000000 CKE_DELAY 2:0 0x0 0x0-0x7 Additional cycles to delay CKE for status reporting CONF_CTL_28[63:32] Offset: 0x1C0 DDR2 667:0x00000001 UB_DIMM 0:0 0x0 0x0-0x1 Enable unbuffered DIMM Table 12. DDR SDRAM configuration parameter register format (continued) Parameters Bits Default value Range Description |
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