 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STLS2F02 数据表(PDF) 31 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLS2F02 数据表(HTML) 31 Page - STMicroelectronics |
|
|
31 / 49 page  STLS2F02 DDR2 SDRAM controller interface description 31/49 DLL_DQS_DELAY_7 38:32 0x0 0x0-0x7F Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 7 during reads. CONF_CTL_12[31:0] Offset: 0xC0 DDR2 667:0x0E000000 TRAS_MIN 31:24 0x0 0x0-0xFF DRAM TRAS_MIN parameter in cycles. OUT_OF_RANGE_LENGTH 23:16 0x0 0x0-0xFF Length f cmd that caused an Out-of- Range interrupt. READ-ONLY ECC_U_SYND 15:8 0x0 0x0-0xFF Syndrome for uncorrectable ECC event. READ-ONLY ECC_C_SYND 7:0 0x0 0x0-0xFF Syndrome for correctable ECC event. READ-ONLY CONF_CTL_12[63:32] Offset: 0xC0 DDR2 667:0x002A3305 DLL_DQS_DELAY_BYPASS_0 56:48 0x0 0x0-0x1FF Number of delay elements to include in the dqs signal from the DRAMs for dll_rd_dqs_slice 0 during reads when DLL is being bypassed. TRFC 47:40 0x0 0x0-0xFF DRAM TRFC parameter in cycles. TRCD_INT 39:32 0x0 0x0-0xFF DRAM TRCD parameter in cycles. CONF_CTL_13[31:0] Offset: 0xD0 DDR2 667:0x002A002A DLL_DQS_DELAY_BYPASS_2 24:16 0x0 0x0-0x1 Number of delay elements to include in the dqs signal from the DRAMs for dll_rd_dqs_slice 2 during reads when DLL is being bypassed. DLL_DQS_DELAY_BYPASS_1 8:0 0x0 0x0-0x1 Number of delay elements to include in the dqs signal from the DRAMs for dll_rd_dqs_slice 1 during reads when DLL is being bypassed. CONF_CTL_13[63:32] Offset: 0xD0 DDR2 667:0x002A002A DLL_DQS_DELAY_BYPASS_4 56:48 0x0 0x0-0x1FF Number of delay elements to include in the dqs signal from the DRAMs for dll_rd_dqs_slice 4 during reads when DLL is being bypassed. DLL_DQS_DELAY_BYPASS_3 40:32 0x0 0x0-0x1FF Number of delay elements to include in the dqs signal from the DRAMs for dll_rd_dqs_slice 3 during reads when DLL is being bypassed. CONF_CTL_14[31:0] Offset: 0xE0 DDR2 667:0x002A002A DLL_DQS_DELAY_BYPASS_6 24:16 0x0 0x0-0x1FF Number of delay elements to include in the dqs signal from the DRAMs for dll_rd_dqs_slice 6 during reads when DLL is being bypassed. Table 12. DDR SDRAM configuration parameter register format (continued) Parameters Bits Default value Range Description |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
