STLS2F02 datasheet(37/49 Pages) STMICROELECTRONICS

37 / 49 page

STLS2F02

Initialization process

37/49

Initialization process

The initialization of STLS2F02 is divided into core and interface parts.

When the STLS2F02 PCI interface is configured as main bridge, interface initialization is

finished internally and PCI_RESETn is output signal. When the processor works as a

PCI/PCIX device, PCI_RESETn acts as an input to reset the STLS2F02 PCI interface.

When the processor reset signal SYSRESETn is low, the related clock, test, and initial

signals must be valid.

●

SYSCLK, MEMCLK, CLKSEL and PCI_CLK must be stable

●

Initial signal PCI_CONFIG should set to the appropriate value

●

TEST_CTRL[7:0] are all high

When SYSRESETn is invalid, the processor internal reset logic begins to work to initialize

the chip. The SYSRESETn signal should be valid for at least one clock cycle to ensure that

it is sampled by the reset logic.

The work mode of the PCI bus is determined by the main bridge during the reset period. The

PCI_RESETn output generated by the processor when it works as the main bridge is used

to ensure that all devices working at the same mode. When not in main bridge mode, the

PCI_RESETn input receives the bus configuration.

Figure 10.

Initialization process when in main bridge mode

PCI_CLK

PCICONFIG

PCI_RESETn

MEMCLK

TESTCTRL

SYSRESETn

SYSCLK

64K SYSCLK

1ms

STLS2F02 数据表(PDF) 37 Page - STMicroelectronics