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STLS2F02 数据表(PDF) 32 Page - STMicroelectronics

部件名 STLS2F02
功能描述  Loongson 2F high performance 64-bit superscalar MIPS® microprocessor
PDF  49 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLS2F02 数据表(HTML) 32 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F02
32/49
DLL_DQS_DELAY_BYPASS_5
8:0
0x0
0x0-0x1FF
Number of delay elements to include in
the dqs signal from the DRAMs for
dll_rd_dqs_slice 7 during reads when
DLL is being bypassed.
CONF_CTL_14[63:32]
Offset: 0xE0
DDR2 667:0x002A002A
DLL_DQS_DELAY_BYPASS_8
56:48
0x0
0x0-0x1FF
Number of delay elements to include in
the dqs signal from the DRAMs for
dll_rd_dqs_slice 8 during reads when
DLL is being bypassed.
DLL_DQS_DELAY_BYPASS_7
40:32
0x0
0x0-0x1FF
Number of delay elements to include in
the dqs signal from the DRAMs for
dll_rd_dqs_slice 7 during reads when
DLL is being bypassed.
CONF_CTL_15[31:0]
Offset: 0xF0
DDR2 667:0x00000004
DLL_LOCK
24:16
0x0
0x0-0x1FF
Number of delay elements in master
DLL lock. READ-ONLY
DLL_INCREMENT
8:0
0x0
0x0-0x1FF
Number of elements to add to
DLL_START_POINT when searching
for lock.
CONF_CTL_15[63:32]
Offset: 0xF0
DDR2 667:0x00B4000A
DQS_OUT_SHIFT_BYPASS
56:48
0x0
0x0-0x1FF
Number of delay elements to include in
the write dqs signal to the DRAMs
during writes when DLL is being
bypassed.
DLL_START_POINT
40:32
0x0
0x0-0x1FF
Initial delay count when searching for
lock in master DLL.
CONF_CTL_16[31:0]
Offset: 0x100
DDR2 667:0x00000087
INT_ACK
25:16
0x0
0x0-0x3FF
Clear mask of the INT_STATUS
parameter. WRITE-ONLY
WR_DQS_SHIFT_BYPASS
8:0
0x0
0x0-0x1FF
Number of delay elements to include in
the clk_wr signal in the controller when
DLL is being bypassed.
CONF_CTL_16[63:32]
Offset: 0x100
DDR2 667:0x00000000
INT_STATUS
58:48
0x0
0x0-0x7FF
Status of interrupt features in the
controller. READ-ONLY
INT_MASK
42:32
0x0
0x0-0x7FF
Mask for controller_int signals from the
INT_STATUS parameter.
CONF_CTL_17[31:0]
Offset: 0x110
DDR2 667:0X0000181B
EMRS1_DATA
30:16
0x0
0x0-0x7FF
EMRS1 data.
TREF
13:0
0x0
0x0-0x3FF
DRAM TREF parameter in cycles.
CONF_CTL_17[63:32]
Offset: 0x110
DDR2 667:0x00000000
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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