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STLS2F02 数据表(PDF) 33 Page - STMicroelectronics

部件名 STLS2F02
功能描述  Loongson 2F high performance 64-bit superscalar MIPS® microprocessor
PDF  49 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLS2F02 数据表(HTML) 33 Page - STMicroelectronics

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STLS2F02
DDR2 SDRAM controller interface description
33/49
EMRS2_DATA_1
62:48
0x0000
0x0-0x7FFF
EMRS2 data for chip select 1.
EMRS2_DATA_0
46:32
0x0000
0x0-0x7FFF
EMRS2 data for chip select 0.
CONF_CTL_18[31:0]
Offset: 0x120
DDR2 667:0x00000000
EMRS2_DATA_3
30:16
0x0000
0x0-0x7FFF
EMRS2 data for chip select 3.
EMRS2_DATA_2
14:0
0x0000
0x0-0x7FFF
EMRS2 data for chip select 2.
CONF_CTL_18[63:32]
Offset: 0x120
DDR2 667:0x001C0000
AXI0_EN_SIZE_LT_WIDTH_INSTR
63:48
0x0000
0x0-0xFFFF
Allow narrow instructions from port 0
requestors with bit enabled.
EMRS3_DATA
46:32
0x0000
0x0-0x7FFF
EMRS3 data.
CONF_CTL_19[31:0]
Offset: 0x130
DDR2 667:0x00C8006B
TDLL
31:16
0x0000
0x0-0xFFFF
DRAM TDLL parameter in cycles.
TCPD
15:0
0x0000
0x0-0xFFFF
DRAM TCPD parameter in cycles.
CONF_CTL_19[63:32]
Offset: 0x130
DDR2 667:0x48E10002
TRAS_MAX
63:48
0x0000
0x0-0xFFFF
DRAM TRAS_MAX parameter in
cycles.
TPDEX
47:32
0x0000
0x0-0xFFFF
DRAM TPDEX parameter in cycles.
CONF_CTL_20[31:0]
Offset: 0x140
DDR2 667:0x00C8002F
TXSR
31:16
0x0000
0x0-0xFFFF
DRAM TXSR parameter in cycles.
TXSNR
15:0
0x0000
0x0-0xFFFF
DRAM TXSNR parameter in cycles.
CONF_CTL_20[63:32]
Offset: 0x140
DDR2 667:0x00000000
XOR_CHECK_BITS
63:48
0x0000
0x0-0xFFFF
Value to Xor with generated ECC
codes for forced write check.
VERSION
47:32
0x2041
0x2041
Controller version number.
READ-ONLY
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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