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STLS2F02 数据表(PDF) 41 Page - STMicroelectronics |
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STLS2F02 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 49 page ![]() STLS2F02 Electrical characteristics 41/49 Table 19. Input setup and hold time (Test conditions:SYSCLK=100 MHz, PCICLK=66 MHz, CoreClk=1000 MHz) Parameter Min Typ Max Unit PCI_* signals setup time 3.0 ns PCI_* signals hold time 0.0 ns LIO_* signals setup time 3.0 ns LIO_* signals hold time 0.0 ns Table 20. Output delay time (Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, CoreClk=1000 MHz) Parameter Min Typ Max Unit PCI_* signals effective delay 0.7 3.8 ns LIO_* signals effective delay 1.5 6.0 ns DDDR2_A*/RAS*/CAS*/WE*/CS*/CKE*/ODT* signals effective delay 1.5 ns DDR2_DQ*/DQM* effective delay 0.75 ns Table 21. JTAG parameters (Test condition:TCK=100 MHz) Parameter Min Typ Max Unit TCK high level time 2 5 8 ns TCK low level time 2 8 ns TCK rising time 1 1 ns TCK falling time 1 1 ns TRST pulse width 10 ns TDI,TMS setup time 3.5 4.4 ns TDI,TMS hold time 2.5 5.5 ns TDO output effective delay 1.28 ns TDO output disable delay 1.28 ns |
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