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STLS2F02 数据表(PDF) 34 Page - STMicroelectronics |
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STLS2F02 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 49 page ![]() DDR2 SDRAM controller interface description STLS2F02 34/49 CONF_CTL_21[31:0] Offset: 0x150 DDR2 667:0x00000036 ECC_C_ADDR[7:0] 31:24 0x0000 0x0- 0x1FFFFFFFF Address of correctable ECC event. READ-ONLY TINIT 23:0 0x0000 0x0-0xFFFFF DRAM TINIT parameter in cycles. CONF_CTL_21[63:32] Offset: 0x150 DDR2 667:0x00000000 ECC_C_ADDR[36:8] 60:32 0x0 0x0- 0x1FFFFFFFF Address of correctable ECC event. READ-ONLY CONF_CTL_22[31:0] Offset: 0x160 DDR2 667:0x00000000 ECC_U_ADDR[31:0] 31:0 0x0 0x0- 0x1FFFFFFFF Address of uncorrectable ECC event. READ-ONLY CONF_CTL_22[63:32] Offset: 0x160 DDR2 667:0x00000000 ECC_U_ADDR[36:32] 36:32 0x0 0x0- 0x1FFFFFFFF Address of uncorrectable ECC event. rEAD-ONLY CONF_CTL_23[31:0] Offset: 0x170 DDR2 667:0x00000000 OUT_OF_RANGE_ADDR[31:0] 31:0 0x0 0x0- 0x1FFFFFFFF Address of cmd that caused an Out-of- Range interrupt. READ-ONLY CONF_CTL_23[63:32] Offset: 0x170 DDR2 667:0x00000000 OUT_OF_RANGE_ADDR[36:32] 36:32 0x0 0x0- 0x1FFFFFFFF Address of cmd that caused an Out-of- Range interrupt. READE-ONLY CONF_CTL_24[31:0] Offset: 0x180 DDR2 667:0x00000000 PORT_CMD_ERROR_ADDR[31:0] 31:0 0x0 0x0- 0x1FFFFFFFF Address of port that caused the PORT cmd error. READ-ONLY CONF_CTL_24[63:32] Offset: 0x180 DDR2 667:0x00000000 PORT_CMD_ERROR_ADDR[36:32] 36:32 0x0 0x0- 0x1FFFFFFFF Address of port that caused the PORT cmd error. READ-ONLY CONF_CTL_25[31:0] Offset: 0x190 DDR2 667:0x00000000 ECC_C_DATA[31:0] 31:0 0x0 0x0- 0x1FFFFFFFF Data associated with correctable ECC event. READ-ONLY CONF_CTL_25[63:32] Offset: 0x190 DDR2 667:0x00000000 ECC_C_DATA[63:32] 63:32 0x0 0x0- 0x1FFFFFFFF Data associated with correctable ECC event. READ-ONLY CONF_CTL_26[31:0] Offset: 0x1A0 DDR2 667:0x00000000 ECC_U_DATA[31:0] 31:0 0x0 0x0- 0x1FFFFFFFF Data associated with uncorrectable ECC event. READ-ONLY CONF_CTL_26[63:32] Offset: 0x1A0 DDR2 667:0x00000000 ECC_U_DATA[63:32] 63:32 0x0 0x0- 0x1FFFFFFFF Data associated with uncorrectable ECC event. READ-ONLY Table 12. DDR SDRAM configuration parameter register format (continued) Parameters Bits Default value Range Description |
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