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STLS2F02 数据表(PDF) 44 Page - STMicroelectronics |
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STLS2F02 数据表(HTML) 44 Page - STMicroelectronics |
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44 / 49 page  Pin arrangement and package information STLS2F02 44/49 8 Pin arrangement and package information 8.1 Pin arrangement The STLS2F02 processor is packaged in HSFCBGA452. The pin arrangement is shown in Figure 12: Pin arrangement (left-hand side), and Figure 14: Pin arrangement (right-hand side), Figure 12. Pin arrangement (left-hand side) gn gnde vd vdd vdd gnd gnde vdd gnd gnde gnd gnde pll_vdd_ dd_1 gpio3 pll pllio_vdd dde1v8 pll_gnd_ l_gnd_1 pll_vdde1v8_ vdde1v8_1 pll_gn _gnde_1 gpio1 pllio_gn o_gnd pllllio_vd o_vdd pllio_gnd o_gnde vdd pll_gnde_ l_gnde_0 gn gnde gn gnde 9 vdd gn gnde pll_gnd_ _gnd_0 pll_vdde1v8_ vdde1v8_0 J gn gnde pll_vdd_ l_vdd_0 gn gnde gn gnde K gn gnde L vdd M vdd vdd N vdd vdd vdde dde3v3 P vdd vdde dde3v3 R vdd T vdd U gn gnde gn gnde 9 vdd gnd gnde vdd gnd gnde vdd gnd gnde gn gnde vdd vdd Core and I/O ground balls Core and I/O ground balls Core power balls Core power balls Color legend Color legend PLL power and ground balls PLL power and ground balls 3.3 V I/O power balls 3.3 V I/O power balls 1 2 3 4 5 6 7 8 9 A gnde vdd TEST_CTRL7 LIO_AD01 LIO_AD04 LIO_AD12 LIO_A3 LIO_A5 LIO_A7 B vdd gnde TEST_CTRL5 TEST_CTRL6 LIO_AD05 LIO_AD08 LIO_A1 LIO_A4 sysclk C vdd TEST_CTRL3 gnde memclk SYSRESETN LIO_AD06 LIO_AD14 LIO_A0 testclk D TEST_CTRL0 TEST_CTRL1 TEST_CTRL2 gnde pllclock1 LIO_AD02 LIO_AD10 LIO_AD09 pllclock0 E pll_vdd_1 gpio0 gpio2 gpio3 F pllio_vdde1v8 pll_gnd_1 pll_vdde1v8_1 pll_gnde_1 G gpio1 pllio_gnd pllio_vdd pllio_gnde H vdd pll_gnde_0 gnde gnde 9 J vdd gnde pll_gnd_0 pll_vdde1v8_0 J gnde K CLKSEL7 pll_vdd_0 gnde gnde K gnde L CLKSEL6 CLKSEL5 CLKSEL8 CLKSEL9 L vdd M CLKSEL3 CLKSEL4 CLKSEL0 CLKSEL2 M vdd N vdd CLKSEL1 PCI_CONFIG7 PCI_CONFIG6 N vdd P vdd PCI_CONFIG5 PCI_CONFIG4 vdde3v3 P vdd R PCI_CONFIG3 PCI_CONFIG0 PCI_CONFIG1 vdde3v3 R vdd T PCI_CONFIG2 PCI_IDSEL PCI_AD00 PCI_AD02 T vdd U PCI_AD01 PCI_AD03 PCI_AD05 PCI_AD04 U gnde V PCI_CBEn0 PCI_AD06 PCI_AD07 PCI_AD08 V gnde W PCI_AD10 PCI_AD09 PCI_AD12 PCI_AD14 9 Y GND PCI_AD11 PCI_AD13 PCI_CBEn1 AA PCI_AD15 PCI_PA R PCI_SERR PCI_FRAMEn AB PCI_PERR PCI_STOPn PCI_IRDYn VDD AC PCI_TRDYn PCI_DEVSELn vdd gnde PCI_AD19 PCI_AD22 PCI_AD28 PCI_AD30 PCI_GNTn5 AD vdd PCI_CBEn2 gnde PCI_AD17 PCI_AD23 PCI_AD24 PCI_AD27 PCI_GNTn6 PCI_REQn5 AE vdd gnde PCI_AD16 PCI_AD18 PCI_AD21 PCI_AD26 PCI_AD31 PCI_REQn6 PCI_GNTn3 AF gnde vdd vdd PCI_AD20 PCI_CBEn3 PCI_AD25 PCI_AD29 PCI_REQn4 PCI_GNTn4 1 2 3 4 5 6 7 8 9 Core and I/O ground balls Core power balls Color legend PLL power and ground balls 3.3 V I/O power balls |
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