H8SLASH3021 datasheet(122/712 Pages) RENESAS

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5. Interrupt Controller

Rev.2.00 Mar. 22, 2007 Page 98 of 684

REJ09B0352-0200

• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

• When the interrupt controller receives one or more interrupt requests, it selects the highest-

priority request, following the IPR interrupt priority settings, and holds other requests pending.

If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt

controller follows the priority order shown in table 5.3.

• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request

is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held

pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is

saved indicates the address of the first instruction that will be executed after the return from the

interrupt service routine.

• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.

• The vector address of the accepted interrupt is generated, and the interrupt service routine

starts executing from the address indicated by the contents of the vector address.

UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ

IRQ

1, IRQ4, and IRQ5 interrupts and interrupts from the on-chip supporting modules.

• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked

when the I bit is cleared to 0.

• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and

are unmasked when either the I bit or the UI bit is cleared to 0.

For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to

H'10, and IPRB is set to H'00 (giving IRQ

4 and IRQ5 interrupt requests priority over other

interrupts), interrupts are masked as follows:

a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ

4 > IRQ5

>IRQ

0 …).

b. If I = 1 and UI = 0, only NMI, IRQ

4, and IRQ5 are unmasked.

c. If I = 1 and UI = 1, all interrupts are masked except NMI.

Figure 5.5 shows the transitions among the above states.

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