H8SLASH3021 datasheet(120/712 Pages) RENESAS

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5. Interrupt Controller

Rev.2.00 Mar. 22, 2007 Page 96 of 684

REJ09B0352-0200

5.4

Interrupt Operation

5.4.1

Interrupt Handling Process

The H8/3022 Group handles interrupts differently depending on the setting of the UE bit. When

UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and

UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I,

and UI bits.

NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts

and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests

are ignored when the enable bits are cleared to 0.

Table 5.4

UE, I, and UI Bit Settings and Interrupt Handling

SYSCR

CCR

Description

—

All interrupts are accepted. Interrupts with priority level 1 have

higher priority.

—

No interrupts are accepted except NMI.

—

All interrupts are accepted. Interrupts with priority level 1 have

higher priority.

NMI and interrupts with priority level 1 are accepted.

No interrupts are accepted except NMI.

UE = 1: Interrupts IRQ

0, IRQ1, IRQ4, and IRQ5 and interrupts from the on-chip supporting

modules can all be masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is

set to 1, and unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher

priority. Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1.

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