H8SLASH3021 datasheet(117/712 Pages) RENESAS

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5. Interrupt Controller

Rev.2.00 Mar. 22, 2007 Page 93 of 684

REJ09B0352-0200

Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).

IRQn

IRQnF

input pin

Note: n = 5, 4, 1 and 0

Figure 5.3 Timing of Setting of IRQnF

Interrupts IRQ

5, IRQ4, IRQ1, IRQ0 have vector numbers 17, 16, 13, 12. These interrupts are

detected regardless of whether the corresponding pin is set for input or output. When using a pin

for external interrupt input, clear its DDR bit to 0 and do not use the pin for SCI input or output.

5.3.2

Internal Interrupts

Twenty-five internal interrupts are requested from the on-chip supporting modules.

• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits

for enabling or disabling interrupts.

• Interrupt priority levels can be assigned in IPRA and IPRB.

5.3.3

Interrupt Vector Table

Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the

default priority order, smaller vector numbers have higher priority. The priority of interrupts other

than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order

shown in table 5.3.

H8/3021 数据表(PDF) 117 Page - Renesas Technology Corp