H8SLASH3021 datasheet(114/712 Pages) RENESAS

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5. Interrupt Controller

Rev.2.00 Mar. 22, 2007 Page 90 of 684

REJ09B0352-0200

5.2.4

IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that enables or disables IRQ

0, IRQ1, IRQ4, and IRQ5

interrupt requests.

Bit

Initial value

Read/Write

—

R/W

These bits enable or disable

IRQ5 and IRQ4 interrupts

—

R/W

IRQ5E

R/W

IRQ4E

R/W

—

R/W

—

R/W

IRQ1E

R/W

IRQ0E

R/W

IRQ to IRQ enable

These bits enable or disable

IRQ1 and IRQ0 interrupts

IRQ to IRQ enable

Reserved bits

IER is initialized to H'00 by a reset and in hardware standby mode.

Bits 7, 6, 3, and 2—Reserved: These bits can be written and read, but they do not enable or

disable interrupts.

Bits 5, 4, 1, and 0—IRQ

5, IRQ4, IRQ1, and IRQ0 Enable (IRQ5E, IRQ4E, IRQ1E, IRQ0E):

These bits enable or disable IRQ

5, IRQ4, IRQ1, IRQ0 interrupts.

Bits 5, 4, 1, and 0

IRQ5E, IRQ4E, IRQ1E,

and IRQ0E

Description

IRQ

5, IRQ4, IRQ1, IRQ0 interrupts are disabled

(Initial value)

IRQ

5, IRQ4, IRQ1, IRQ0 interrupts are enabled

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