SH7708 datasheet(429/633 Pages) RENESAS

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Table 14.7

Maximum Bit Rates for Frequencies (Smart Card Interface Mode)

φ (MHz)

Maximum Bit Rate (Bit/s)

7.1424

9600

10.00

13441

10.7136

14400

13.00

17473

14.2848

19200

16.00

21505

18.00

24194

The bit rate error is found as follows:

Error(%) = (

× 106 – 1) × 100

1488

× 22n–1 × B × (N + 1)

Table 14.8 shows the relationship between transmit/receive clock register set values and output

states on the smart card interface.

Table 14.8

SCK Pin

Setting

SMIF

CKE1

CKE0

Output

State

1*1

1000

Port

Determined by setting of port

bits

1001

SCK (serial clock) output state

2*2

1100

Low output

Low output state

1101

SCK (serial clock) output state

3*2

1110

High output

High output state

1111

SCK (serial clock) output state

Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit

should be cleared to 0.

2. The clock duty remains constant despite stopping and starting of the clock by

modification of the CKE0 bit.

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