SH7708 datasheet(13/633 Pages) RENESAS

13 / 633 page

8.7.1

Transition to Hardware Standby Mode ................................................................ 153

8.7.2

Canceling Hardware Standby Mode .................................................................... 154

8.7.3

Hardware Standby Mode Timing ......................................................................... 154

Section 9 On-Chip Oscillation Circuits ......................................................................... 157

9.1

Overview............................................................................................................................ 157

9.1.1

Features ................................................................................................................ 157

9.2

Overview of the CPG ........................................................................................................ 158

9.2.1

CPG Block Diagram............................................................................................. 158

9.2.2

CPG Pin Configuration ........................................................................................ 161

9.2.3

CPG Register Configuration ................................................................................ 161

9.3

Clock Operating Modes ..................................................................................................... 162

9.4

Register Descriptions......................................................................................................... 170

9.4.1

Frequency Control Register (FRQCR) ................................................................. 170

9.5

Changing the Frequency.................................................................................................... 174

9.5.1

Changing the Multiplication Rate ........................................................................ 174

9.5.2

Changing the Division Ratio ................................................................................ 174

9.6

PLL Standby Function....................................................................................................... 175

9.6.1

Overview of the PLL Standby Function .............................................................. 175

9.6.2

Usage .................................................................................................................... 175

9.7

Controlling Clock Output .................................................................................................. 176

9.7.1

Clock Modes 0–2.................................................................................................. 176

9.7.2

Clock Modes 3 and 4............................................................................................ 176

9.8

Overview of the Watchdog Timer (WDT) ........................................................................ 177

9.8.1

Block Diagram of the WDT ................................................................................. 177

9.8.2

9.9

WDT Registers .................................................................................................................. 178

9.9.1

Watchdog Timer Counter (WTCNT) ................................................................... 178

9.9.2

Watchdog Timer Control/Status Register (WTCSR) ........................................... 178

9.9.3

Notes on Register Access ..................................................................................... 180

9.10

Using the WDT.................................................................................................................. 181

9.10.1 Canceling Standbys .............................................................................................. 181

9.10.2 Changing the Frequency....................................................................................... 181

9.10.3 Using Watchdog Timer Mode.............................................................................. 182

9.10.4 Using Interval Timer Mode.................................................................................. 182

9.10.5 Usage Notes.......................................................................................................... 183

9.11

Notes on Board Design...................................................................................................... 184

Section 10 Bus State Controller (BSC) ......................................................................... 187

10.1

Overview............................................................................................................................ 187

10.1.1 Features ................................................................................................................ 187

10.1.2 Block Diagram...................................................................................................... 188

10.1.3 Pin Configuration ................................................................................................. 190

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