SH7708 datasheet(31/633 Pages) RENESAS

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Section 2 CPU

2.1

2.1.1

Privileged Mode and Banks

Processor Modes: There are two processor modes: user mode and privileged mode. The SH7708

Series normally operates in user mode, and enters privileged mode when an exception occurs or an

interrupt is accepted. There are three kinds of registers—general registers, system registers, and

control registers—and the registers that can be accessed differ in the two processor modes.

General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to

R7 are banked registers which are switched by a processor mode change. In privileged mode, the

general registers, and which set is accessed only through the load control register (LDC) and store

control register (STC) instructions.

When the RB bit is 1, BANK1 general registers R0_BANK1–R7_BANK1 and non-banked

general registers R8–R15 function as the general register set, with BANK0 general registers

R0_BANK0–R7_BANK0 accessed only by the LDC/STC instructions.

When the RB bit is 0, BANK0 general registers R0_BANK0–R7_BANK0 and nonbanked general

registers R8–R15 function as the general register set, with BANK1 general registers R0_BANK1–

R7_BANK1 accessed only by the LDC/STC instructions. In user mode, the 16 registers

comprising bank 0 general registers R0_BANK0–R7_BANK0 and non-banked registers R8–R15

can be accessed as general registers R0–R15, and bank 1 general registers R0_BANK1–

R7_BANK1 cannot be accessed.

Control Registers: Control registers comprise the global base register (GBR) and status register

(SR) which can be accessed in both processor modes, and the saved status register (SSR), saved

program counter (SPC), and vector base register (VBR) which can only be accessed in privileged

mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged

mode.

System Registers: System registers comprise the multiply and accumulate registers

(MACL/MACH), the procedure register (PR), and the program counter (PC). Access to these

registers does not depend on the processor mode.

The register configuration in each mode is shown in figures 2.1 and 2.2.

Switching between user mode and privileged mode is controlled by the processor mode bit (MD)

in the status register.

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