SH7708 datasheet(77/633 Pages) RENESAS

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The MMU registers are shown in figure 3.3.

VPN

PTEH

PTEL

ASID

PPN

4 3 2 1 0

TTB

Virtual address causing TLB-related

or address error exception

TEA

PR SZ C D

SH 0

MMUCR

73 2 1

0 TF IX AT

0: Reserved bits (except MMUCR): Always read as 0. Writing is ignored.

(MMUCR) :Except bit 3 is read as 0. Bit 3 is don't care. Writing is

should be 0.

SV: Single virtual memory mode bit. Set to 1 for single virtual memory mode, cleared

to 0 for multiple virtual memory mode.

RC: A 2-bit random counter, automatically updated by hardware according to the

following rules in the event of an MMU exception. When a TLB miss exception

occurs, all TLB entry ways corresponding to the virtual address at which the

exception occurred are checked, and if all ways are valid, 1 is added to RC; if

there is one or more invalid way, they are set by priority from way 0, in the order:

way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB

miss exception, the way which caused the exception is set in RC.

TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always

IX: Index mode bit. When 0, VPN bits 16–12 are used as the TLB index number.

When 1, the value obtained by EX-ORing ASID bits 4–0 in PTEH and VPN bits

16–12 are used as the TLB index number.

AT: Address translation bit. Enables/disables the MMU.

0: MMU disabled

Figure 3.3 MMU Register Contents

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