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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 83 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 83 Page - Renesas Technology Corp |
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83 / 633 page  65 3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception. For physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. To record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. The C bit in the entry indicates whether the referenced page resides in a cacheable or non- cacheable area of memory. The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions. Access states designated by the D, C, and PR bits are shown in table 3.2. Table 3.2 Access States Designated by D, C, and PR Bits Privileged Mode User Mode Reading Writing Reading Writing D bit 0 Permitted Initial page write exception Permitted Initial page write exception 1 Permitted Permitted Permitted Permitted C bit 0 Permitted (no caching) Permitted (no caching) Permitted (no caching) Permitted (no caching) 1 Permitted (with caching) Permitted (with caching) Permitted (with caching) Permitted (with caching) PR bit 00 Permitted TLB protection violation exception TLB protection violation exception TLB protection violation exception 01 Permitted Permitted TLB protection violation exception TLB protection violation exception 10 Permitted TLB protection violation exception Permitted TLB protection violation exception 11 Permitted Permitted Permitted Permitted |
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