SH7708 datasheet(74/633 Pages) RENESAS

74 / 633 page

Physical Address Space: The SH7708 Series supports a 32-bit physical address space, but the

upper 3 bits are actually ignored and treated as a shadow. See section 10, Bus State Controller, for

details.

Single Address Translation: When the MMU is enabled, the virtual address space is divided into

units called pages. Physical addresses are translated in page units. Address translation tables in

external memory hold information such as the physical address that corresponds to the virtual

address and memory protection codes. With the TLB, the contents of address translation tables in

external memory are cached to speed up address translation. When an access to areas P1 or P2

occurs, there is no TLB access and the physical address is defined uniquely by the hardware. If it

belongs to areas P0, P3 or U0, the TLB is searched by virtual address and, if that virtual address is

registered in the TLB, the access hits the TLB. The corresponding physical address and the page

control information are read from the TLB and the physical address is determined.

If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing

will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in

external memory is searched and the corresponding physical address and the page control

information are registered in the TLB. After returning from the handler, the instruction that caused

the TLB miss is re-executed. When the MMU is enabled, address translation information that

results in a physical address space of H'80000000–H'FFFFFFFF should not be registered in the

TLB.

When the MMU is disabled, the virtual address is used directly as the physical address. As the

SH7708 Series supports a 29-bit address space as the physical address space, the top 3 bits of the

physical address are ignored, and constitute a shadow space (see section 10, Bus State Controller

(BSC)). For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area,

H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical

address. When access to these addresses is performed with the cache enabled, an address with the

top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data

congruity.

Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual

memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual

memory mode, multiple processes run in parallel using the virtual address space exclusively and

the physical address corresponding to a given virtual address is specified uniquely. In multiple

virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a

given virtual address may be translated into different physical addresses depending on the process.

Either single or multiple virtual mode is selected according to the value set in the MMU control

address used to access external memory is compared with the VPN of the TLB entry selected by

the index number.

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