SH7708 datasheet(54/633 Pages) RENESAS

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Table 2.7

Arithmetic Instructions (cont)

Instruction

Operation

Code

Privileged

Mode

Cycles T Bit

DMULS.L Rm,Rn

Signed operation of

× Rm → MACH,

MACL 32

× 32 → 64 bits

0011nnnnmmmm1101

—

2(–5)*

—

DMULU.L Rm,Rn

Unsigned operation of

× Rm → MACH,

MACL 32

× 32 → 64 bits

0011nnnnmmmm0101

—

2(–5)*

—

Rn – 1

→ Rn, if Rn =

0, 1

→ T, else 0 → T

0100nnnn00010000

—

Comparison

result

EXTS.B Rm,Rn

A byte in Rm is sign-

extended

→ Rn

0110nnnnmmmm1110

—1

—

EXTS.W Rm,Rn

A word in Rm is sign-

extended

→ Rn

0110nnnnmmmm1111

—1

—

EXTU.B Rm,Rn

A byte in Rm is zero-

extended

→ Rn

0110nnnnmmmm1100

—1

—

EXTU.W Rm,Rn

A word in Rm is zero-

extended

→ Rn

0110nnnnmmmm1101

—1

—

MAC.L

@Rm+,@Rn+

Signed operation of (Rn)

× (Rm) + MAC → MAC,

Rn + 4

→ Rn,

Rm + 4

→ Rm

× 32 + 64 → 64 bits

0000nnnnmmmm1111

—

2(–5)*

—

MAC.W

@Rm+,@Rn+

Signed operation of (Rn)

× (Rm) + MAC → MAC,

Rn + 2

→ Rn,

Rm + 2

→ Rm

× 16 + 64 → 64 bits

0100nnnnmmmm1111

—

2(–5)*

—

MUL.L

Rm,Rn

× Rm → MACL

× 32 → 32 bits

0000nnnnmmmm0111

—

2(–5)*

—

MULS.W Rm,Rn

Signed operation of Rn

× Rm → MAC

× 16 → 32 bits

0010nnnnmmmm1111

—

1(–3)*

—

MULU.W Rm,Rn

Unsigned operation of

× Rm → MAC

× 16 → 32 bits

0010nnnnmmmm1110

—

1(–3)*

—

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