SH7708 datasheet(60/633 Pages) RENESAS

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Table 2.11

System Control Instructions (cont)

Instruction

Operation

Code

Privileged

Mode

Cycles T Bit

LDC.L @Rm+,

R4_BANK

(Rm)

→ R4_BANK,

Rm + 4

→ Rm

0100mmmm11000111

√

1—

LDC.L @Rm+,

R5_BANK

(Rm)

→ R5_BANK,

Rm + 4

→ Rm

0100mmmm11010111

√

1—

LDC.L @Rm+,

R6_BANK

(Rm)

→ R6_BANK,

Rm + 4

→ Rm

0100mmmm11100111

√

1—

LDC.L @Rm+,

R7_BANK

(Rm)

→ R7_BANK,

Rm + 4

→ Rm

0100mmmm11110111

√

1—

LDS

Rm,MACH

→ MACH

0100mmmm00001010

—1

—

LDS

Rm,MACL

→ MACL

0100mmmm00011010

—1

—

LDS

Rm,PR

→ PR

0100mmmm00101010

—1

—

LDS.L @Rm+,MACH

(Rm)

→ MACH, Rm + 4 → Rm

0100mmmm00000110

—1

—

LDS.L @Rm+,MACL

(Rm)

→ MACL, Rm + 4 → Rm

0100mmmm00010110

—1

—

LDS.L @Rm+,PR

(Rm)

→ PR, Rm + 4 → Rm

0100mmmm00100110

—1

—

LDTLB

PTEH/PTEL

→ TLB

0000000000111000

√

1—

NOP

No operation

0000000000001001

—1

—

PREF

@Rm

(Rm)

→ cache

0000mmmm10000011

—

1—

RTE

Delayed branch,

SSR/SPC

→ SR/PC

0000000000101011

√

4—

SETS

→ S

0000000001011000

—1

—

SETT

→ T

0000000000011000

—1

SLEEP

Sleep

0000000000011011

√

—

STC

SR,Rn

→ Rn

0000nnnn00000010

√

1—

STC

GBR,Rn

GBR

→ Rn

0000nnnn00010010

—1

—

STC

VBR,Rn

VBR

→ Rn

0000nnnn00100010

√

1—

STC

SSR,Rn

SSR

→ Rn

0000nnnn00110010

√

1—

STC

SPC,Rn

SPC

→ Rn

0000nnnn01000010

√

1—

STC

R0_BANK,Rn

R0_BANK

→ Rn

0000nnnn10000010

√

1—

STC

R1_BANK,Rn

R1_BANK

→ Rn

0000nnnn10010010

√

1—

STC

R2_BANK,Rn

R2_BANK

→ Rn

0000nnnn10100010

√

1—

STC

R3_BANK,Rn

R3_BANK

→ Rn

0000nnnn10110010

√

1—

Note: * The number of cycles until the sleep state is entered.

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