SH7708 datasheet(67/633 Pages) RENESAS

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From any state except

hardware standby mode when

RESET = 0 and BREQ = 1

From any state except

hardware standby mode when

RESET = 0 and BREQ = 0

RESET = 1,

BREQ = 1

RESET = 1,

BREQ = 0

RESET = 0,

BREQ = 1

Power-on reset

state

Manual reset

state

Program execution state

Note: * Driving the CA pin low in any state will cause a transition to hardware standby mode (SH7708S,SH7708R only).

Bus-released state

Sleep mode

Standby mode

Exception-handling state

Hardware standby mode*

Interrupt

Bus

request

Bus

request

clearance

Exception

interrupt

End of exception

transition

processing

Bus

request

Bus

request

clearance

SLEEP

instruction

with STBY

bit set

Interrupt

Reset state

Power-down state

CA = 1,

RESET = 0, BREQ = 1

SLEEP

instruction

with STBY

bit cleared

Bus

request

Bus

request

clearance

Figure 2.8 Processor State Transitions

2.5.2

Processor Modes

There are two processor modes: privileged mode and user mode. The processor mode is

determined by the processor mode bit (MD) in the status register (SR). User mode is selected

when the MD bit is 0, and privileged mode when the MD bit is 1. When the reset state or

exception state is entered, the MD bit is set to 1. When exception handling ends, the MD bit is

cleared to 0 and user mode is entered. There are certain registers and bits which can only be

accessed in privileged mode.

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