SH7708 datasheet(11/633 Pages) RENESAS

11 / 633 page

iii

5.1.1

Features ................................................................................................................

5.1.2

Cache Structure ....................................................................................................

5.1.3

5.2

Register Description ..........................................................................................................

5.2.1

Cache Control Register (CCR) .............................................................................

5.3

Cache Operation ................................................................................................................ 100

5.3.1

Searching the Cache ............................................................................................. 100

5.3.2

Read Access.......................................................................................................... 102

5.3.3

Write Access ........................................................................................................ 102

5.3.4

Write-Back Buffer................................................................................................ 102

5.3.5

Coherency of Cache and External Memory ......................................................... 103

5.3.6

RAM Mode .......................................................................................................... 103

5.4

Memory-Mapped Cache .................................................................................................... 103

5.4.1

Address Array ...................................................................................................... 103

5.4.2

Data Array ............................................................................................................ 104

5.5

Usage Examples ................................................................................................................ 106

5.5.1

Invalidating Specific Entries ................................................................................ 106

5.5.2

Reading the Data of a Specific Entry ................................................................... 106

Section 6 Interrupt Controller (INTC) ........................................................................... 107

6.1

Overview............................................................................................................................ 107

6.1.1

Features ................................................................................................................ 107

6.1.2

Block Diagram...................................................................................................... 108

6.1.3

Pin Configuration ................................................................................................. 109

6.1.4

6.2

Interrupt Sources................................................................................................................ 109

6.2.1

NMI Interrupts...................................................................................................... 110

6.2.2

IRL Interrupts ....................................................................................................... 110

6.2.3

On-Chip Supporting Module Interrupts ............................................................... 112

6.2.4

Interrupt Exception Handling and Priority ........................................................... 112

6.3

INTC Registers .................................................................................................................. 115

6.3.1

Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 115

6.3.2

Interrupt Control Register (ICR) .......................................................................... 116

6.4

INTC Operation ................................................................................................................. 117

6.4.1

Interrupt Sequence................................................................................................ 117

6.4.2

Multiple Interrupts................................................................................................ 119

6.5

Interrupt Response Time.................................................................................................... 120

Section 7 User Break Controller (UBC)........................................................................ 123

7.1

Overview............................................................................................................................ 123

7.1.1

Features ................................................................................................................ 123

7.1.2

Block Diagram...................................................................................................... 123

7.1.3

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