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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 462 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 462 Page - Renesas Technology Corp |
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462 / 633 page  444 16.3.2 Control Signal Timing Table 16.8 Control Signal Timing (VCC = 3.3 ± 0.3 V, Ta = –20 to + 75°C) –60*2 Item Symbol Min Max Unit Figure RESET pulse width tRESW 20 — tcyc 16.11, 16.13, RESET setup time tRESS 23 — ns 16.15 RESET hold time tRESH 2— ns BREQ setup time tBREQS 12 — ns BREQ hold time tBREQH 3— ns BREQ reset setup time tBREQRS 17 — ns BREQ reset hold time tBREQRH 16 — ns MD reset setup time tMDRS 20 — tcyc 16.12 MD reset hold time tMDRH 16 — ns NMI setup time*1 tNMIS 15 — ns 16.13 IRL3–IRL0 setup time*1 tIRLS 10 — ns NMI hold time tNMIH 4— ns IRL3–IRL0 hold time tIRLH 4— ns IRQOUT delay time tIRQOD — 12 ns 16.14 BACK delay time tBACKD — 12 ns 16.15, 16.16 STATUS1, STATUS0 delay time tSTD —16 ns Bus tri-state delay time 1 tBOFF1 016 ns Bus tri-state delay time 2 tBOFF2 016 ns Bus buffer on time 1 tBON1 016 ns Bus buffer on time 2 tBON2 016 ns Notes: 1. RESET, NMI, and IRL3 to IRL0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock fall. 2. Upper limit of external bus clock is 60 MHz. |
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